公开(公告)号：US20150171097A1

公开(公告)日：2015-06-18

申请号：US14484977

申请日：2014-09-12

Applicant: JEEHOON HAN ,  YOON HEE KIM ,  JI SUN PARK ,  WANGCHUL SHIN

Inventor： JEEHOON HAN ,  YOON HEE KIM ,  JI SUN PARK ,  WANGCHUL SHIN

IPC: H01L27/115 ,  H01L29/49 ,  H01L29/788 ,  H01L29/423

CPC classification number: H01L27/11524 ,  H01L27/11529 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: A nonvolatile memory device has select gates on a semiconductor substrate and cell gates on the semiconductor substrate between the select gates. Each of the cell gates includes a floating gate pattern on the semiconductor substrate, a tunnel insulating pattern interposed between the floating gate pattern and the semiconductor substrate, a blocking insulating pattern on the floating gate pattern, and a control gate pattern on the blocking insulating pattern. The control gate pattern includes a first control gate pattern, a second control gate pattern on the first control gate pattern, a cell conductive pattern on the second control gate pattern, and a barrier pattern interposed between the first control gate pattern and the second control gate pattern. Each of the select gates may have patterns similar to those of the cell gates.

Abstract translation: 非易失性存储器件在半导体衬底上具有选择栅极，并且在选择栅极之间具有半导体衬底上的栅极。 每个单元栅极包括半导体衬底上的浮置栅极图案，插入在浮置栅极图案和半导体衬底之间的隧道绝缘图案，浮动栅极图案上的阻挡绝缘图案以及阻挡绝缘图案上的控制栅极图案 。 控制栅极图案包括第一控制栅极图案，第一控制栅极图案上的第二控制栅极图案，第二控制栅极图案上的单元导电图案，以及介于第一控制栅极图案和第二控制栅极之间的势垒图案 模式。 每个选择栅极可以具有与单元栅极类似的图案。

公开(公告)号：US20190148295A1

公开(公告)日：2019-05-16

申请号：US16247712

申请日：2019-01-15

Applicant: Sung-Hun Lee ,  Seokjung Yun ,  Chang-Sup Lee ,  Seong Soon Cho ,  Jeehoon Han

Inventor： Sung-Hun Lee ,  Seokjung Yun ,  Chang-Sup Lee ,  Seong Soon Cho ,  Jeehoon Han

IPC: H01L23/528 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/522 ,  H01L27/11578 ,  H01L21/768 ,  H01L27/11565 ,  H01L27/11551 ,  H01L27/11556

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

公开(公告)号：US20170179028A1

公开(公告)日：2017-06-22

申请号：US15350305

申请日：2016-11-14

Applicant: Sung-Hun Lee ,  Seokjung Yun ,  Chang-Sup Lee ,  Seong Soon Cho ,  Jeehoon Han

Inventor： Sung-Hun Lee ,  Seokjung Yun ,  Chang-Sup Lee ,  Seong Soon Cho ,  Jeehoon Han

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/115

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.