公开(公告)号：US20190148295A1

公开(公告)日：2019-05-16

申请号：US16247712

申请日：2019-01-15

申请人： Sung-Hun Lee ,  Seokjung Yun ,  Chang-Sup Lee ,  Seong Soon Cho ,  Jeehoon Han

发明人： Sung-Hun Lee ,  Seokjung Yun ,  Chang-Sup Lee ,  Seong Soon Cho ,  Jeehoon Han

IPC分类号： H01L23/528 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/522 ,  H01L27/11578 ,  H01L21/768 ,  H01L27/11565 ,  H01L27/11551 ,  H01L27/11556

摘要： A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

公开(公告)号：US20170179028A1

公开(公告)日：2017-06-22

申请号：US15350305

申请日：2016-11-14

申请人： Sung-Hun Lee ,  Seokjung Yun ,  Chang-Sup Lee ,  Seong Soon Cho ,  Jeehoon Han

发明人： Sung-Hun Lee ,  Seokjung Yun ,  Chang-Sup Lee ,  Seong Soon Cho ,  Jeehoon Han

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/115

CPC分类号： H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

摘要： A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

公开(公告)号：US10032791B2

公开(公告)日：2018-07-24

申请号：US15403779

申请日：2017-01-11

申请人： Chang-Sup Lee ,  Sung-Hun Lee ,  Joonhee Lee ,  Seong Soon Cho

发明人： Chang-Sup Lee ,  Sung-Hun Lee ,  Joonhee Lee ,  Seong Soon Cho

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L23/535 ,  H01L27/11556 ,  H01L29/423

CPC分类号： H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L29/42328 ,  H01L29/42344

摘要： A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.

公开(公告)号：US20170207238A1

公开(公告)日：2017-07-20

申请号：US15403779

申请日：2017-01-11

申请人： Chang-Sup Lee ,  Sung-Hun Lee ,  Joonhee Lee ,  Seong Soon Cho

发明人： Chang-Sup Lee ,  Sung-Hun Lee ,  Joonhee Lee ,  Seong Soon Cho

IPC分类号： H01L27/11582 ,  H01L23/535 ,  H01L23/528 ,  H01L29/423 ,  H01L27/11556 ,  H01L23/522

CPC分类号： H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L29/42328 ,  H01L29/42344

摘要： A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.

公开(公告)号：US10482964B2

公开(公告)日：2019-11-19

申请号：US16040837

申请日：2018-07-20

申请人： Da Woon Jeong ,  Sung-Hun Lee ,  Seokjung Yun ,  Hyunmog Park ,  JoongShik Shin ,  Young-Bae Yoon

发明人： Da Woon Jeong ,  Sung-Hun Lee ,  Seokjung Yun ,  Hyunmog Park ,  JoongShik Shin ,  Young-Bae Yoon

IPC分类号： G11C16/04 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  G11C5/02 ,  G11C5/06 ,  H01L49/02

摘要： Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region. Each of the intermediate stack structures exposes the third stair step structure of the intermediate stack structure disposed thereunder.

公开(公告)号：US10049744B2

公开(公告)日：2018-08-14

申请号：US15383213

申请日：2016-12-19

申请人： Da Woon Jeong ,  Sung-Hun Lee ,  Seokjung Yun ,  Hyunmog Park ,  JoongShik Shin ,  Young-Bae Yoon

发明人： Da Woon Jeong ,  Sung-Hun Lee ,  Seokjung Yun ,  Hyunmog Park ,  JoongShik Shin ,  Young-Bae Yoon

IPC分类号： H01L29/788 ,  G11C16/04 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  G11C5/02 ,  G11C5/06

摘要： Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region. Each of the intermediate stack structures exposes the third stair step structure of the intermediate stack structure disposed thereunder.

公开(公告)号：US20110254077A1

公开(公告)日：2011-10-20

申请号：US13079382

申请日：2011-04-04

申请人： Chang-Sup Lee ,  Jongho Park ,  Sung-Hun Lee ,  Ki-Yong Kim

发明人： Chang-Sup Lee ,  Jongho Park ,  Sung-Hun Lee ,  Ki-Yong Kim

IPC分类号： H01L29/78

CPC分类号： H01L27/11529 ,  H01L27/11548

摘要： A semiconductor device includes a plurality of gate structures disposed on a substrate. Respective gate structures may include a lower control gate layer and an upper control gate layer. The upper control gate layer may be disposed on the lower control gate layer and may include a different material from the lower control gate layer. The semiconductor device may further include insulation patterned layers disposed in gap regions defined between the gate structures adjacent to each other. Upper surfaces of the insulation patterned layers may be lower than an upper surface of the lower control gate layer.

摘要翻译： 半导体器件包括设置在衬底上的多个栅极结构。 各个栅极结构可以包括下部控制栅极层和上部控制栅极层。 上部控制栅极层可以设置在下部控制栅极层上，并且可以包括与下部控制栅极层不同的材料。 半导体器件还可以包括设置在彼此相邻的栅极结构之间限定的间隙区域中的绝缘图案化层。 绝缘图案化层的上表面可以低于下控制栅层的上表面。

公开(公告)号：US08827536B2

公开(公告)日：2014-09-09

申请号：US13820053

申请日：2013-02-22

申请人： Gun-Hwan Lee ,  Jung-Heum Yun ,  Sung-Hun Lee

发明人： Gun-Hwan Lee ,  Jung-Heum Yun ,  Sung-Hun Lee

IPC分类号： F21V8/00 ,  G09F13/22 ,  G09F9/00 ,  F21V21/00 ,  H04M1/02

CPC分类号： H05K5/0234 ,  F21V21/00 ,  G09F9/00 ,  G09F13/22 ,  H04M1/0202 ,  H04M1/0268 ,  H04M1/0283 ,  H05K5/0017

摘要： In one embodiment, the display device includes a display panel and a support frame. The display panel includes a flexible upper substrate, at least one light emitting diode, and a flexible lower substrate (30). The display panel has a display area formed at a portion corresponding to the light emitting diode, and a non-display area formed at a portion other than the display area. The display panel is coupled to the support frame such that a portion of the non-display area is bent with respect to the display area.

摘要翻译： 在一个实施例中，显示装置包括显示面板和支撑框架。 显示面板包括柔性上基板，至少一个发光二极管和柔性下基板（30）。 显示面板具有形成在与发光二极管相对应的部分的显示区域和形成在显示区域以外的部分的非显示区域。 显示面板联接到支撑框架，使得非显示区域的一部分相对于显示区域弯曲。

公开(公告)号：US20140126228A1

公开(公告)日：2014-05-08

申请号：US13820053

申请日：2013-02-22

申请人： Gun-Hwan Lee ,  Jung-Heum Yun ,  Sung-Hun Lee

发明人： Gun-Hwan Lee ,  Jung-Heum Yun ,  Sung-Hun Lee

IPC分类号： F21V21/00

CPC分类号： H05K5/0234 ,  F21V21/00 ,  G09F9/00 ,  G09F13/22 ,  H04M1/0202 ,  H04M1/0268 ,  H04M1/0283 ,  H05K5/0017

摘要： In one embodiment, the display device includes a display panel and a support frame. The display panel includes a flexible upper substrate, at least one light emitting diode, and a flexible lower substrate (30). The display panel has a display area formed at a portion corresponding to the light emitting diode, and a non-display area formed at a portion other than the display area. The display panel is coupled to the support frame such that a portion of the non-display area is bent with respect to the display area.

摘要翻译： 在一个实施例中，显示装置包括显示面板和支撑框架。 显示面板包括柔性上基板，至少一个发光二极管和柔性下基板（30）。 显示面板具有形成在与发光二极管相对应的部分的显示区域和形成在显示区域以外的部分的非显示区域。 显示面板联接到支撑框架，使得非显示区域的一部分相对于显示区域弯曲。

公开(公告)号：US08648526B2

公开(公告)日：2014-02-11

申请号：US12929841

申请日：2011-02-18

申请人： Sung-Hun Lee ,  Jung-Bae Song

发明人： Sung-Hun Lee ,  Jung-Bae Song

IPC分类号： H01J1/62 ,  H01J63/04

CPC分类号： H01L27/3258 ,  H01L27/3206 ,  H01L27/3211 ,  H01L27/322 ,  H01L51/5265 ,  H01L51/5284

摘要： An organic light emitting display apparatus includes a substrate, a color filter layer on the substrate, a transflective reflective layer on the color filter layer, the transflective reflective layer being configured to partly transmit and partly reflect visible light, a first electrode on the transflective reflective layer, an intermediate layer on the first electrode, the intermediate layer including an organic emission layer, a second electrode on the intermediate layer, and an optical path control layer (OPCL) between the transflective reflective layer and the first electrode, the OPCL including an insulating material and being configured to control a path of light generated in the intermediate layer.

摘要翻译： 一种有机发光显示装置，包括基板，基板上的滤色器层，滤色器层上的透反射反射层，透反射反射层被配置为部分地透射和部分地反射可见光，半透反射反射层上的第一电极 层，第一电极上的中间层，中间层包括有机发光层，中间层上的第二电极和透反射反射层与第一电极之间的光路控制层（OPCL），OPCL包括 并且被配置为控制在中间层中产生的光的路径。