公开(公告)号：US08694755B1

公开(公告)日：2014-04-08

申请号：US12725899

申请日：2010-03-17

申请人： Kathirgamar Aingaran ,  Leslie D. Kohn ,  Robert C. Kunz ,  Jenn-Yuan Tsai

发明人： Kathirgamar Aingaran ,  Leslie D. Kohn ,  Robert C. Kunz ,  Jenn-Yuan Tsai

IPC分类号： G06F12/10

CPC分类号： G06F12/0284 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/651

摘要： An apparatus comprising an arbiter circuit, a translation circuit and a controller circuit. The arbiter circuit may be configured to generate one or more first control signals and a data write signal in response to an input signal and a read data signal. The translation circuit may be configured to generate a one or more second control signals in response to the one or more first control signals and the write address signal. The controller circuit may be configured to generate an address signal in response to the one or more second control signals.

摘要翻译： 一种包括调节器电路，平移电路和控制器电路的装置。 仲裁器电路可以被配置为响应于输入信号和读取数据信号而产生一个或多个第一控制信号和数据写入信号。 翻译电路可以被配置为响应于一个或多个第一控制信号和写入地址信号而产生一个或多个第二控制信号。 控制器电路可以被配置为响应于一个或多个第二控制信号而产生地址信号。

公开(公告)号：US07290116B1

公开(公告)日：2007-10-30

申请号：US10881714

申请日：2004-06-30

申请人： Greg F. Grohoski ,  Manish Shah ,  John D. Davis ,  Ashley Saulsbury ,  Cong Fu ,  Venkatesh Iyengar ,  Jenn-Yuan Tsai ,  Jeff Gibson

发明人： Greg F. Grohoski ,  Manish Shah ,  John D. Davis ,  Ashley Saulsbury ,  Cong Fu ,  Venkatesh Iyengar ,  Jenn-Yuan Tsai ,  Jeff Gibson

IPC分类号： G06F12/00

CPC分类号： G06F12/0811 ,  G06F12/0864

摘要： An apparatus and method for mapping memory addresses to reduce or avoid conflicting memory accesses in memory systems such as cache memories is described in connection with a multithreaded multiprocessor chip. A CMT processor reduces the probability of hot-spots in cache operations by hashing certain bits of a physical cache address to form a hashed cache address. By using exclusive OR functionality to hash the index bits, an efficient address transformation is achieved for indexing into an L2 cache memory.

摘要翻译： 结合多线程多处理器芯片描述了用于映射存储器地址以减少或避免诸如高速缓冲存储器的存储器系统中的冲突存储器访问的装置和方法。 CMT处理器通过对物理缓存地址的某些位进行散列来形成一个散列缓存地址来降低高速缓存操作中热点的概率。 通过使用异或功能对索引位进行散列，实现了高效的地址转换，用于索引到L2高速缓存中。

公开(公告)号：US06807627B2

公开(公告)日：2004-10-19

申请号：US09765930

申请日：2001-01-19

申请人： Jenn-Yuan Tsai ,  Vinodha Ramasamy

发明人： Jenn-Yuan Tsai ,  Vinodha Ramasamy

IPC分类号： G06F9312

CPC分类号： G06F9/461 ,  G06F11/3636 ,  G06F11/3648

摘要： Techniques are disclosed for preserving first content in a first register. In one embodiment, the first register is a general register, a second register is a UNaT register, and each general register is associated with a NaT bit. To preserve the content of the UNaT register while saving the content of a general register and its associated NaT bit, the content of the general register is saved to a floating-point register, and the NaT bit associated with the general register is also saved. If the NaT bit is set, then only the NaT bit is restored. Conversely, if the NaT bit is not set, then both the content of the general register and the NaT bit are restored.

摘要翻译： 公开了用于在第一寄存器中保存第一内容的技术。 在一个实施例中，第一寄存器是通用寄存器，第二寄存器是UNaT寄存器，每个通用寄存器与一个NaT位相关联。 为了保存UNaT寄存器的内容，同时保存通用寄存器及其关联的NaT位的内容，通用寄存器的内容将保存到浮点寄存器，并且与通用寄存器相关联的NaT位也被保存。 如果NaT位被置位，则仅恢复NaT位。 相反，如果NaT位未设置，则通用寄存器的内容和NaT位都将被恢复。

公开(公告)号：US09600412B1

公开(公告)日：2017-03-21

申请号：US13008287

申请日：2011-01-18

申请人： Kathirgamar Aingaran ,  Leslie D. Kohn ,  Robert C. Kunz ,  Jenn-Yuan Tsai

发明人： Kathirgamar Aingaran ,  Leslie D. Kohn ,  Robert C. Kunz ,  Jenn-Yuan Tsai

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/02 ,  G06F12/10

CPC分类号： G06F12/0284 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/651

摘要： An arbiter circuit and a translation circuit. The arbiter circuit may be configured to generate a first address signal in a virtual memory space by arbitrating among a plurality of clients to access a physical memory space. The clients may be classified as either privileged clients or non-privileged clients. The physical memory space may comprise at least one secure space. The secure space may be used to protect data of the privileged clients from being accessed by the non-privileged clients. The translation circuit may be configured to generate a second address signal by translating a page in the virtual memory space into the physical memory space. The page may correspond to a particular one of the clients that won the arbitration. The page may translate into the secure space if the particular client is one of the privileged clients. The page may also translate outside the secure space if the particular client is one of the non-privileged clients.

公开(公告)号：US07107579B2

公开(公告)日：2006-09-12

申请号：US10143429

申请日：2002-05-09

申请人： Jenn-Yuan Tsai ,  Vinodha Ramasamy

发明人： Jenn-Yuan Tsai ,  Vinodha Ramasamy

IPC分类号： G06F9/44

CPC分类号： G06F9/4484

摘要： Method and apparatus for preserving program context when causing execution of a probe routine from a target routine of an executable computer program code. Executable code for the probe routine is created such that the probe routine does not reference a first set of registers that are usable by the target routine. A modified version of the target routine is created to cause execution of the probe routine. The modified version of the target routine is performed instead of the original version when the target routine is called during program execution. A second set of registers on the processor register stack is allocated when the probe routine is invoked. The second set of registers is not manipulated by the probe routine so as to avoid changing contents of registers of the register stack that are used by the target routine.

公开(公告)号：US06931632B2

公开(公告)日：2005-08-16

申请号：US10005302

申请日：2001-11-08

申请人： Vinodha Ramasamy ,  Jenn-Yuan Tsai

发明人： Vinodha Ramasamy ,  Jenn-Yuan Tsai

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/44 ,  G06F9/45 ,  G06F15/00

CPC分类号： G06F9/30054 ,  G06F9/30072 ,  G06F9/3842 ,  G06F9/3853

摘要： Method and apparatus for instrumentation of an executable computer program that includes a predicated branch-call instruction followed by a call-shadow instruction. The predicated branch-call instruction and the call-shadow instruction is stored in a first bundle of instructions, which is followed by a second bundle. The predicated branch-call instruction is changed to a predicated branch instruction that targets a fifth bundle of instructions, and the predicate of the predicated branch instruction is the same as the predicate of the predicated branch-call instruction. Third, fourth, and fifth bundles are created to preserve program semantics. The third bundle is inserted following the first bundle and includes the call-shadow instruction. The fourth bundle is inserted following the third bundle and includes a branch instruction that targets the second bundle. The fifth bundle is inserted following the fourth bundle and includes a branch-call instruction that has a target address equal to the target address of the predicated branch-call instruction. Instrumentation instructions are then inserted.

摘要翻译： 用于仪器化可执行计算机程序的方法和装置，其包括一个预先指派的分支调用指令，后跟一个调用 - 阴影指令。 预测的分支调用指令和调用指令被存储在第一指令束中，随后是第二束。 预测的分支调用指令被改变为目标第五指令束的预测分支指令，并且预测分支指令的谓词与预测分支调用指令的谓词相同。 创建第三，第四和第五个包以保留程序语义。 第三个软件包按照第一个软件包插入，并包含调用阴影指令。 第四个捆绑包插入第三个捆绑包之后，并包括一个分支指令，目标是第二个捆绑包。 第五束被插入到第四束之后，并且包括具有等于预测分支呼叫指令的目标地址的目标地址的分支调用指令。 然后插入仪器说明。