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公开(公告)号：US20070252254A1
公开(公告)日：2007-11-01
申请号：US11414526
申请日：2006-04-28
Applicant: Chin-Tien Chiu , Hem Takiar , Hui Liu , Jiang hua Java Zhu , Jack Chang-Chien , Cheemen Yu
Inventor： Chin-Tien Chiu , Hem Takiar , Hui Liu , Jiang hua Java Zhu , Jack Chang-Chien , Cheemen Yu
IPC: H01L23/02
CPC classification number: H01L23/562 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/49109 , H01L2225/06562 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H05K3/303 , H05K3/3421 , H05K3/3484 , H05K2201/09781 , H05K2201/10689 , H05K2201/2036 , H05K2203/041 , H05K2203/043 , Y02P70/613 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: An integrated circuit, and a semiconductor die package formed therefrom, are disclosed including solder columns for adding structural support to the package during the fabrication process.
Abstract translation: 公开了集成电路和由其形成的半导体管芯封装，其包括用于在制造工艺期间向封装件添加结构支撑的焊料柱。
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公开(公告)号：US08878346B2
公开(公告)日：2014-11-04
申请号：US11414526
申请日：2006-04-28
Applicant: Chin-Tien Chiu , Hem Takiar , Hui Liu , Jiang Hua Java Zhu , Jack Chang-Chien , Cheemen Yu
Inventor： Chin-Tien Chiu , Hem Takiar , Hui Liu , Jiang Hua Java Zhu , Jack Chang-Chien , Cheemen Yu
IPC: H01L23/495 , H05K3/30 , H05K3/34 , H01L23/00
CPC classification number: H01L23/562 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/49109 , H01L2225/06562 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H05K3/303 , H05K3/3421 , H05K3/3484 , H05K2201/09781 , H05K2201/10689 , H05K2201/2036 , H05K2203/041 , H05K2203/043 , Y02P70/613 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: An integrated circuit, and a semiconductor die package formed therefrom, are disclosed including solder columns for adding structural support to the package during the fabrication process.
Abstract translation: 公开了一种集成电路和由其形成的半导体管芯封装，其包括用于在制造工艺期间向封装件添加结构支撑的焊料柱。
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3.发明授权Method of reducing mechanical stress on a semiconductor die during fabrication 有权在制造期间减小半导体管芯上的机械应力的方法公开(公告)号：US07435624B2
公开(公告)日：2008-10-14
申请号：US11414780
申请日：2006-04-28
Applicant: Chin-Tien Chiu , Hem Takiar , Hui Liu , Jiang hua Java Zhu , Jack Chang-Chien , Cheemen Yu
Inventor： Chin-Tien Chiu , Hem Takiar , Hui Liu , Jiang hua Java Zhu , Jack Chang-Chien , Cheemen Yu
IPC: H01L21/44
CPC classification number: H05K3/303 , H05K3/284 , H05K2201/0305 , H05K2201/09781 , H05K2201/10689 , H05K2201/2036 , H05K2203/1316 , Y02P70/613
Abstract: A method of reducing mechanical stress on an integrated circuit is disclosed including applying solder columns to the substrate for adding structural support to the package during the fabrication process.
Abstract translation: 公开了一种降低集成电路上的机械应力的方法，包括在制造过程中将焊料柱施加到衬底以增加对封装的结构支撑。
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