公开(公告)号：US07403056B2

公开(公告)日：2008-07-22

申请号：US11562473

申请日：2006-11-22

申请人： Jingran Qu ,  Zhongding Liu ,  Chun-Fu Lin

发明人： Jingran Qu ,  Zhongding Liu ,  Chun-Fu Lin

IPC分类号： H03H11/26

CPC分类号： H03L7/0814

摘要： The present invention provides a delay apparatus for delaying an input signal by a predetermined delay amount, including: a plurality of delay units for respectively delaying the input signal by the predetermined delay amount, each delay unit having a plurality of delay cells for respectively delaying the input signal by a certain delay period; and a sub decoding unit for generating a plurality of sub control signals to each of the delay units according to a first control signal and a selecting signal, wherein only delay cell of all the delay units is outputted at a time according to the sub controls signals.

摘要翻译： 本发明提供了一种用于将输入信号延迟预定延迟量的延迟装置，包括：用于分别将输入信号延迟预定延迟量的多个延迟单元，每个延迟单元具有多个延迟单元，用于分别延迟 输入信号一定的延迟时间; 以及副解码单元，用于根据第一控制信号和选择信号向每个延迟单元生成多个子控制信号，其中只有根据子控制信号一次输出所有延迟单元的延迟单元 。

公开(公告)号：US07525363B2

公开(公告)日：2009-04-28

申请号：US11834075

申请日：2007-08-06

申请人： Zhongding Liu ,  Jingran Qu

发明人： Zhongding Liu ,  Jingran Qu

IPC分类号： H03H11/26

CPC分类号： H03L7/0814

摘要： A delay line comprises first and second delay arrays and a multiplexer. The first delay array receives a clock signal and a delay control signal, and delays the clock signal to output a first delay array clock signal according to the delay control signal. The second delay array receives a power control signal, the first delay array clock signal and the delay control signal. The second delay array is turned on or off according to the power control signal. If the second delay array is turned on, the second delay array delays the first delay array clock signal to output a second delay array clock signal according to the delay control signal. The multiplexer receives a selecting control signal, the first and second delay array clock signals, and outputs the first delay array clock signal or the second delay array clock according to the selecting control signal.

摘要翻译： 延迟线包括第一和第二延迟阵列和多路复用器。 第一延迟阵列接收时钟信号和延迟控制信号，并延迟时钟信号以根据延迟控制信号输出第一延迟阵列时钟信号。 第二延迟阵列接收功率控制信号，第一延迟阵列时钟信号和延迟控制信号。 第二延迟阵列根据功率控制信号而导通或关断。 如果第二延迟阵列导通，则第二延迟阵列延迟第一延迟阵列时钟信号，以根据延迟控制信号输出第二延迟阵列时钟信号。 多路复用器接收选择控制信号，第一和第二延迟阵列时钟信号，并根据选择控制信号输出第一延迟阵列时钟信号或第二延迟阵列时钟。

公开(公告)号：US20090085621A1

公开(公告)日：2009-04-02

申请号：US12102107

申请日：2008-04-14

申请人： Zhongding Liu ,  Jingran Qu

发明人： Zhongding Liu ,  Jingran Qu

IPC分类号： H03L7/06 ,  H03B1/04

CPC分类号： H03L7/093

摘要： Loop filters are provided, in which a first resistor comprises a first terminal coupled to a first node, and a second terminal coupled to a second node; a first capacitor is coupled between the second node and a ground voltage, a second resistor comprises a first terminal coupled to the first node and a second terminal coupled to a third node. An operational amplifier comprises a non-inversion input terminal coupled to the second node, an inversion input terminal coupled to the third node, and an output terminal, and a second capacitor is coupled between the output terminal of the operational amplifier and the third node.

摘要翻译： 提供了环路滤波器，其中第一电阻器包括耦合到第一节点的第一端子和耦合到第二节点的第二端子; 第一电容器耦合在第二节点和接地电压之间，第二电阻器包括耦合到第一节点的第一终端和耦合到第三节点的第二终端。 运算放大器包括耦合到第二节点的非反相输入端子，耦合到第三节点的反相输入端子和输出端子，并且第二电容器耦合在运算放大器的输出端子和第三节点之间。

公开(公告)号：US20080116948A1

公开(公告)日：2008-05-22

申请号：US11562473

申请日：2006-11-22

申请人： Jingran Qu ,  Zhongding Liu ,  Chun-Fu Lin

发明人： Jingran Qu ,  Zhongding Liu ,  Chun-Fu Lin

IPC分类号： H03L7/06 ,  H03L7/00

CPC分类号： H03L7/0814

摘要： The present invention provides a delay apparatus for delaying an input signal by a predetermined delay amount, including: a plurality of delay units for respectively delaying the input signal by the predetermined delay amount, each delay unit having a plurality of delay cells for respectively delaying the input signal by a certain delay period; and a sub decoding unit for generating a plurality of sub control signals to each of the delay units according to a first control signal and a selecting signal, wherein only delay cell of all the delay units is outputted at a time according to the sub controls signals.

摘要翻译： 本发明提供了一种用于将输入信号延迟预定延迟量的延迟装置，包括：用于分别将输入信号延迟预定延迟量的多个延迟单元，每个延迟单元具有多个延迟单元，用于分别延迟 输入信号一定的延迟时间; 以及副解码单元，用于根据第一控制信号和选择信号向每个延迟单元生成多个子控制信号，其中只有根据子控制信号一次输出所有延迟单元的延迟单元 。

公开(公告)号：US07649408B2

公开(公告)日：2010-01-19

申请号：US12102107

申请日：2008-04-14

申请人： Zhongding Liu ,  Jingran Qu

发明人： Zhongding Liu ,  Jingran Qu

IPC分类号： H03B1/00 ,  H03K5/00

CPC分类号： H03L7/093

摘要： Loop filters are provided, in which a first resistor comprises a first terminal coupled to a first node, and a second terminal coupled to a second node; a first capacitor is coupled between the second node and a ground voltage, a second resistor comprises a first terminal coupled to the first node and a second terminal coupled to a third node. An operational amplifier comprises a non-inversion input terminal coupled to the second node, an inversion input terminal coupled to the third node, and an output terminal, and a second capacitor is coupled between the output terminal of the operational amplifier and the third node.

摘要翻译： 提供了环路滤波器，其中第一电阻器包括耦合到第一节点的第一端子和耦合到第二节点的第二端子; 第一电容器耦合在第二节点和接地电压之间，第二电阻器包括耦合到第一节点的第一终端和耦合到第三节点的第二终端。 运算放大器包括耦合到第二节点的非反相输入端子，耦合到第三节点的反相输入端子和输出端子，并且第二电容器耦合在运算放大器的输出端子和第三节点之间。

公开(公告)号：US20080054958A1

公开(公告)日：2008-03-06

申请号：US11834075

申请日：2007-08-06

申请人： Zhongding Liu ,  Jingran Qu

发明人： Zhongding Liu ,  Jingran Qu

IPC分类号： H03L7/06

CPC分类号： H03L7/0814

摘要： A delay line comprises first and second delay arrays and a multiplexer. The first delay array receives a clock signal and a delay control signal, and delays the clock signal to output a first delay array clock signal according to the delay control signal. The second delay array receives a power control signal, the first delay array clock signal and the delay control signal. The second delay array is turned on or off according to the power control signal. If the second delay array is turned on, the second delay array delays the first delay array clock signal to output a second delay array clock signal according to the delay control signal. The multiplexer receives a selecting control signal, the first and second delay array clock signals, and outputs the first delay array clock signal or the second delay array clock according to the selecting control signal.

摘要翻译： 延迟线包括第一和第二延迟阵列和多路复用器。 第一延迟阵列接收时钟信号和延迟控制信号，并延迟时钟信号以根据延迟控制信号输出第一延迟阵列时钟信号。 第二延迟阵列接收功率控制信号，第一延迟阵列时钟信号和延迟控制信号。 第二延迟阵列根据功率控制信号而导通或关断。 如果第二延迟阵列导通，则第二延迟阵列延迟第一延迟阵列时钟信号，以根据延迟控制信号输出第二延迟阵列时钟信号。 多路复用器接收选择控制信号，第一和第二延迟阵列时钟信号，并根据选择控制信号输出第一延迟阵列时钟信号或第二延迟阵列时钟。