公开(公告)号：US5686843A

公开(公告)日：1997-11-11

申请号：US497126

申请日：1995-06-30

申请人： Kenneth Edward Beilstein, Jr. ,  Claude Louis Bertin ,  Dennis Charles Dubois ,  Wayne John Howell ,  Gordon Arthur Kelley, Jr. ,  Christopher Paul Miller ,  David Jacob Perlman ,  Gustav Schrottke ,  Edmund Juris Sprogis ,  Jody John VanHorn

发明人： Kenneth Edward Beilstein, Jr. ,  Claude Louis Bertin ,  Dennis Charles Dubois ,  Wayne John Howell ,  Gordon Arthur Kelley, Jr. ,  Christopher Paul Miller ,  David Jacob Perlman ,  Gustav Schrottke ,  Edmund Juris Sprogis ,  Jody John VanHorn

IPC分类号： G01R31/26 ,  G01R1/04 ,  G01R31/28 ,  H01L21/66 ,  H01L25/00 ,  G01R31/02

CPC分类号： G01R31/2863 ,  G01R1/0483 ,  G01R31/2851 ,  G01R31/2886 ,  G01R31/2889 ,  H01L2924/0002

摘要： Methods and apparatus are set forth for burn-in stressing and simultaneous testing of a plurality of semiconductor device chips laminated together in a stack configuration to define a multichip module. Testing is facilitated by connecting temporary interconnect wiring to an access surface of the multichip module. This temporary interconnect wiring electrically interconnects at least some semiconductor device chips within the module. Prior to burn-in stressing and testing, a separate electrical screening step occurs to identify any electrical defect in the connection between the temporary interconnect wiring and the multichip module. If an electrical defect is identified, various techniques for removing or isolating the defect are presented. Thereafter, burn-in stressing and simultaneous testing of the semiconductor chips within the multichip module occurs using the temporary interconnect wiring. Various alignment and test fixtures are described for facilitating this burn-in and simultaneous testing of the semiconductor chips within the multichip module.

摘要翻译： 阐述了以堆叠配置层叠在一起的多个半导体器件芯片的老化应力和同时测试方法和装置，以限定多芯片模块。 通过将临时互连线连接到多芯片模块的访问表面来实现测试。 该临时互连布线使模块内的至少一些半导体器件芯片电互连。 在老化应力和测试之前，会发生单独的电气筛选步骤，以识别临时互连线路和多芯片模块之间的连接中的任何电气缺陷。 如果识别出电气缺陷，则提出了用于去除或隔离缺陷的各种技术。 此后，使用临时互连布线发生多芯片模块内的半导体芯片的老化强度和同时测试。 描述了各种对准和测试夹具，以便于该多芯片模块内的半导体芯片的老化和同时测试。

公开(公告)号：US5923181A

公开(公告)日：1999-07-13

申请号：US840041

申请日：1997-04-24

申请人： Kenneth Edward Beilstein, Jr. ,  Claude Louis Bertin ,  Dennis Charles Dubois ,  Wayne John Howell ,  Gordon Arthur Kelley, Jr. ,  Christopher Paul Miller ,  David Jacob Perlman ,  Gustav Schrottke ,  Edmund Juris Sprogis ,  Jody John VanHorn

发明人： Kenneth Edward Beilstein, Jr. ,  Claude Louis Bertin ,  Dennis Charles Dubois ,  Wayne John Howell ,  Gordon Arthur Kelley, Jr. ,  Christopher Paul Miller ,  David Jacob Perlman ,  Gustav Schrottke ,  Edmund Juris Sprogis ,  Jody John VanHorn

IPC分类号： G01R31/26 ,  G01R1/04 ,  G01R31/28 ,  H01L21/66 ,  H01L25/00 ,  G01R31/02

CPC分类号： G01R31/2863 ,  G01R1/0483 ,  G01R31/2851 ,  G01R31/2886 ,  G01R31/2889 ,  H01L2924/0002

摘要： Methods and apparatus are set forth for burn-in stressing and simultaneous testing of a plurality of semiconductor device chips laminated together in a stack configuration to define a multichip module. Testing is facilitated by connecting temporary interconnect wiring to an access surface of the multichip module. This temporary interconnect wiring electrically interconnects at least some semiconductor device chips within the module. Prior to burn-in stressing and testing, a separate electrical screening step occurs to identify any electrical defect in the connection between the temporary interconnect wiring and the multichip module. If an electrical defect is identified, various techniques for removing or isolating the defect are presented. Thereafter, burn-in stressing and simultaneous testing of the semiconductor chips within the multichip module occurs using the temporary interconnect wiring. Various alignment and test fixtures are described for facilitating this burn-in and simultaneous testing of the semiconductor chips within the multichip module.

摘要翻译： 阐述了以堆叠配置层叠在一起的多个半导体器件芯片的老化应力和同时测试方法和装置，以限定多芯片模块。 通过将临时互连线连接到多芯片模块的访问表面来实现测试。 该临时互连布线使模块内的至少一些半导体器件芯片电互连。 在老化应力和测试之前，会发生单独的电气筛选步骤，以识别临时互连线路和多芯片模块之间的连接中的任何电气缺陷。 如果识别出电气缺陷，则提出了用于去除或隔离缺陷的各种技术。 此后，使用临时互连线路进行多芯片模块内的半导体芯片的老化强度和同时测试。 描述了各种对准和测试夹具，以便于该多芯片模块内的半导体芯片的老化和同时测试。