公开(公告)号：US5786628A

公开(公告)日：1998-07-28

申请号：US951663

申请日：1997-10-16

Applicant: Kenneth Edward Beilstein, Jr. ,  Claude Louis Bertin ,  John Edward Cronin ,  Wayne John Howell ,  James Marc Leas ,  David Jacob Perlman

Inventor： Kenneth Edward Beilstein, Jr. ,  Claude Louis Bertin ,  John Edward Cronin ,  Wayne John Howell ,  James Marc Leas ,  David Jacob Perlman

IPC: H01L21/98 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L23/06 ,  H01L23/02

CPC classification number: H01L25/50 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/49107 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/30107

Abstract: A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary support which is used to attach the thin-film layer to the electronic module. The disclosed techniques may also be used for attaching an interposer, which may include active circuity, to an electronic module. Specific details of the fabrication method, resulting multichip packages, and various thin-film structures are set forth.

Abstract translation: 一种具有附接到侧表面的单独形成的薄膜层的制造方法和所得到的单片电子模块。 该制造方法包括提供由堆叠的集成电路芯片组成的电子模块。 在用于将薄膜层附着到电子模块的临时支架上分开形成薄膜层。 所公开的技术还可以用于将可包括有源电路的插入件附接到电子模块。 阐述了制造方法，所得到的多芯片封装以及各种薄膜结构的具体细节。

公开(公告)号：US5719438A

公开(公告)日：1998-02-17

申请号：US469090

申请日：1995-06-06

Applicant: Kenneth Edward Beilstein, Jr. ,  Claude Louis Bertin ,  John Edward Cronin ,  Wayne John Howell ,  James Marc Leas ,  David Jacob Perlman

Inventor： Kenneth Edward Beilstein, Jr. ,  Claude Louis Bertin ,  John Edward Cronin ,  Wayne John Howell ,  James Marc Leas ,  David Jacob Perlman

IPC: H01L21/98 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L23/02 ,  H01L23/04

CPC classification number: H01L25/50 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/49107 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/30107

Abstract: A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary support which is used to attach the thin-film layer to the electronic module. The disclosed techniques may also be used for attaching an interposer, which may include active circuity, to an electronic module. Specific details of the fabrication method, resulting multichip packages, and various thin-film structures are set forth.

公开(公告)号：US5686843A

公开(公告)日：1997-11-11

申请号：US497126

申请日：1995-06-30

Applicant: Kenneth Edward Beilstein, Jr. ,  Claude Louis Bertin ,  Dennis Charles Dubois ,  Wayne John Howell ,  Gordon Arthur Kelley, Jr. ,  Christopher Paul Miller ,  David Jacob Perlman ,  Gustav Schrottke ,  Edmund Juris Sprogis ,  Jody John VanHorn

Inventor： Kenneth Edward Beilstein, Jr. ,  Claude Louis Bertin ,  Dennis Charles Dubois ,  Wayne John Howell ,  Gordon Arthur Kelley, Jr. ,  Christopher Paul Miller ,  David Jacob Perlman ,  Gustav Schrottke ,  Edmund Juris Sprogis ,  Jody John VanHorn

IPC: G01R31/26 ,  G01R1/04 ,  G01R31/28 ,  H01L21/66 ,  H01L25/00 ,  G01R31/02

CPC classification number: G01R31/2863 ,  G01R1/0483 ,  G01R31/2851 ,  G01R31/2886 ,  G01R31/2889 ,  H01L2924/0002

Abstract: Methods and apparatus are set forth for burn-in stressing and simultaneous testing of a plurality of semiconductor device chips laminated together in a stack configuration to define a multichip module. Testing is facilitated by connecting temporary interconnect wiring to an access surface of the multichip module. This temporary interconnect wiring electrically interconnects at least some semiconductor device chips within the module. Prior to burn-in stressing and testing, a separate electrical screening step occurs to identify any electrical defect in the connection between the temporary interconnect wiring and the multichip module. If an electrical defect is identified, various techniques for removing or isolating the defect are presented. Thereafter, burn-in stressing and simultaneous testing of the semiconductor chips within the multichip module occurs using the temporary interconnect wiring. Various alignment and test fixtures are described for facilitating this burn-in and simultaneous testing of the semiconductor chips within the multichip module.

Abstract translation: 阐述了以堆叠配置层叠在一起的多个半导体器件芯片的老化应力和同时测试方法和装置，以限定多芯片模块。 通过将临时互连线连接到多芯片模块的访问表面来实现测试。 该临时互连布线使模块内的至少一些半导体器件芯片电互连。 在老化应力和测试之前，会发生单独的电气筛选步骤，以识别临时互连线路和多芯片模块之间的连接中的任何电气缺陷。 如果识别出电气缺陷，则提出了用于去除或隔离缺陷的各种技术。 此后，使用临时互连布线发生多芯片模块内的半导体芯片的老化强度和同时测试。 描述了各种对准和测试夹具，以便于该多芯片模块内的半导体芯片的老化和同时测试。

公开(公告)号：US5923181A

公开(公告)日：1999-07-13

申请号：US840041

申请日：1997-04-24

Applicant: Kenneth Edward Beilstein, Jr. ,  Claude Louis Bertin ,  Dennis Charles Dubois ,  Wayne John Howell ,  Gordon Arthur Kelley, Jr. ,  Christopher Paul Miller ,  David Jacob Perlman ,  Gustav Schrottke ,  Edmund Juris Sprogis ,  Jody John VanHorn

Inventor： Kenneth Edward Beilstein, Jr. ,  Claude Louis Bertin ,  Dennis Charles Dubois ,  Wayne John Howell ,  Gordon Arthur Kelley, Jr. ,  Christopher Paul Miller ,  David Jacob Perlman ,  Gustav Schrottke ,  Edmund Juris Sprogis ,  Jody John VanHorn

IPC: G01R31/26 ,  G01R1/04 ,  G01R31/28 ,  H01L21/66 ,  H01L25/00 ,  G01R31/02

CPC classification number: G01R31/2863 ,  G01R1/0483 ,  G01R31/2851 ,  G01R31/2886 ,  G01R31/2889 ,  H01L2924/0002

Abstract: Methods and apparatus are set forth for burn-in stressing and simultaneous testing of a plurality of semiconductor device chips laminated together in a stack configuration to define a multichip module. Testing is facilitated by connecting temporary interconnect wiring to an access surface of the multichip module. This temporary interconnect wiring electrically interconnects at least some semiconductor device chips within the module. Prior to burn-in stressing and testing, a separate electrical screening step occurs to identify any electrical defect in the connection between the temporary interconnect wiring and the multichip module. If an electrical defect is identified, various techniques for removing or isolating the defect are presented. Thereafter, burn-in stressing and simultaneous testing of the semiconductor chips within the multichip module occurs using the temporary interconnect wiring. Various alignment and test fixtures are described for facilitating this burn-in and simultaneous testing of the semiconductor chips within the multichip module.

Abstract translation: 阐述了以堆叠配置层叠在一起的多个半导体器件芯片的老化应力和同时测试方法和装置，以限定多芯片模块。 通过将临时互连线连接到多芯片模块的访问表面来实现测试。 该临时互连布线使模块内的至少一些半导体器件芯片电互连。 在老化应力和测试之前，会发生单独的电气筛选步骤，以识别临时互连线路和多芯片模块之间的连接中的任何电气缺陷。 如果识别出电气缺陷，则提出了用于去除或隔离缺陷的各种技术。 此后，使用临时互连线路进行多芯片模块内的半导体芯片的老化强度和同时测试。 描述了各种对准和测试夹具，以便于该多芯片模块内的半导体芯片的老化和同时测试。

公开(公告)号：US5712190A

公开(公告)日：1998-01-27

申请号：US585579

申请日：1996-01-16

Applicant: Claude Louis Bertin ,  John Edward Cronin ,  David Jacob Perlman

Inventor： Claude Louis Bertin ,  John Edward Cronin ,  David Jacob Perlman

IPC: H01L25/00 ,  H01L21/98 ,  H01L23/52 ,  H01L25/065 ,  H01L21/027 ,  H01L21/31

CPC classification number: H01L25/50 ,  H01L25/0657 ,  H01L2224/13022 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/10253 ,  Y10S438/928 ,  Y10S438/975 ,  Y10S438/977

Abstract: Methods for alignment of stacked integrated circuit chips and the resultant three-dimensional semiconductor structures. A thickness control layer is deposited, as needed, on each integrated circuit chip. The thickness of the layer is determined by the thickness of the chip following a grind stage in the fabrication process. Complementary patterns are etched into the thickness control layer of each chip and into adjacent chips. Upon stacking the chips in a three dimensional structure, precise alignment is obtained for interconnect pads which are disposed on the edges of each integrated circuit chip. Dense bus and I/O networks can be thereby supported on a face of the resultant three-dimensional structure.

Abstract translation: 用于堆叠集成电路芯片和所得三维半导体结构的对准的方法。 根据需要在每个集成电路芯片上沉积厚度控制层。 该层的厚度由在制造过程中的研磨阶段之后的芯片的厚度确定。 互补图案蚀刻到每个芯片的厚度控制层中并进入相邻的芯片。 在三维结构中堆叠芯片时，对于布置在每个集成电路芯片的边缘上的互连焊盘，获得精确的对准。 因此，可以在所得到的三维结构的表面上支持密集的总线和I / O网络。