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公开(公告)号：US07050063B1
公开(公告)日：2006-05-23
申请号：US09502994
申请日：2000-02-11
申请人： Michael Mantor , John Austin Carey , Ralph Clayton Taylor , Thomas A. Piazza , Jeffrey D. Potter , Angel E. Socarras
发明人： Michael Mantor , John Austin Carey , Ralph Clayton Taylor , Thomas A. Piazza , Jeffrey D. Potter , Angel E. Socarras
IPC分类号： G09G5/00
CPC分类号： G09G5/39 , G06T1/60 , G06T15/04 , G09G3/003 , G09G2360/121
摘要： A 3D rendering texture caching scheme that minimizes external bandwidth requirements for texture and increases the rate at which textured pixels are available. The texture caching scheme efficiently pre-fetches data at the main memory access granularity and stores it in cache memory. The data in the main memory and texture cache memory is organized in a manner to achieve large reuse of texels with a minimum of cache memory to minimize cache misses. The texture main memory stores a two dimensional array of texels, each texel having an address and one of N identifiers. The texture cache memory has addresses partitioned into N banks, each bank containing texels transferred from the main memory that have the corresponding identifier. A cache controller determines which texels need to be transferred from the texture main memory to the texture cache memory and which texels are currently in the cache using a least most recently used algorithm. By labeling the texture map blocks (double quad words), a partitioning scheme is developed which allow the cache controller structure to be very modular and easily realized. The texture cache arbiter is used for scheduling and controlling the actual transfer of texels from the texture main memory into the texture cache memory and controlling the outputting of texels for each pixel to an interpolating filter from the cache memory.
摘要翻译： 3D渲染纹理缓存方案，可最大限度地减少纹理的外部带宽需求，并提高纹理像素可用的速率。 纹理缓存方案有效地预取主存储器访问粒度的数据并将其存储在高速缓冲存储器中。 主存储器和纹理高速缓冲存储器中的数据被组织成以最小的高速缓冲存储器实现大量的纹理复用的重用，以最小化高速缓存未命中。 纹理主存储器存储纹素的二维阵列，每个纹素具有地址和N个标识符之一。 纹理高速缓冲存储器具有分割成N个存储体的地址，每个存储体包含从主存储器传送的具有相应标识符的纹素。 高速缓存控制器使用最近最少使用的算法来确定哪个纹素需要从纹理主存储器传送到纹理高速缓存存储器以及哪个纹素目前在高速缓存中。 通过标记纹理贴图块（双四字），开发了一种分区方案，允许高速缓存控制器结构非常模块化，轻松实现。 纹理高速缓存仲裁器用于调度和控制纹理主体存储器到纹理高速缓存存储器中的纹素的实际传输，并且控制从高速缓冲存储器输出每个像素的纹理像素到内插滤波器。
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2.发明授权Method and apparatus to efficiently interpolate polygon attributes in two dimensions at a prescribed clock rate 失效以规定的时钟速率有效地在多维属性中插入多边形属性的方法和装置
公开(公告)号：US6072505A
公开(公告)日：2000-06-06
申请号：US53589
申请日：1998-04-01
申请人： Thomas A. Piazza , R. Scott Hartog , Michael Mantor , Jeffrey D. Potter , Ralph Clayton Taylor , Michael A. Mang
发明人： Thomas A. Piazza , R. Scott Hartog , Michael Mantor , Jeffrey D. Potter , Ralph Clayton Taylor , Michael A. Mang
CPC分类号： G06T3/403
摘要： A rasterizer comprised of a bounding box calculator, a plane converter, a windower, and incrementers. For each polygon to be processed, a bounding box calculation is performed which determines the display screen area, in spans, that totally encloses the polygon and passes the data to the plane converter. The plane converter also receives as input attribute values for each vertex of the polygon. The plane converter computes planar coefficients for each attribute of the polygon, for each of the edges of the polygon. The plane converter unit computes the start pixel center location at a start span and a starting coefficient value at that pixel center. The computed coefficients also include the rate of change or gradient, for each polygon attribute in the x and y directions, respectively. The plane converter also computes line coefficients for each of the edges of the polygon. Line equation values are passed through to the windower where further calculations allow the windower to determine which spans are either covered or intersected by the polygon. The incrementers receive the span coverage data from the windower in addition to receiving planar coefficient values from the plane converter. The incrementers utilize the data from both the windower and plane converter to walk or traverse the polygon in those intersected spans, pixel by pixel. As the incrementer visits each pixel, vertex attribute values are interpolated to each pixel.
摘要翻译： 由边界计算器，平面转换器，加窗器和加法器构成的光栅化器。 对于要处理的每个多边形，执行边界框计算，其确定完全包围多边形并将数据传递到平面转换器的跨度的显示屏幕区域。 平面转换器还接收多边形的每个顶点的输入属性值。 平面转换器为多边形的每个边缘计算多边形的每个属性的平面系数。 平面转换器单元计算开始跨度处的开始像素中心位置和该像素中心处的起始系数值。 所计算的系数也分别包括x和y方向上每个多边形属性的变化率或梯度。 平面转换器还为多边形的每个边缘计算线系数。 线路方程值被传递到风力发电机，进一步的计算允许风轮确定哪个跨度被多边形覆盖或相交。 除了从平面转换器接收平面系数值之外，增量器还接收来自风力发电机的跨距覆盖数据。 增量器利用来自两台风力发电机和平面转换器的数据逐行扫描或横穿那些相交的跨度中的多边形。 随着增量器访问每个像素，顶点属性值被内插到每个像素。
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公开(公告)号：US06204857B1
公开(公告)日：2001-03-20
申请号：US09061383
申请日：1998-04-16
IPC分类号： G06T1140
CPC分类号： G06T15/04
摘要： Method and apparatus for rendering texture to an object to be displayed on a pixel screen display. This technique makes use of linear interpolation between perspectively correct texture address to calculate rates of change of individual texture addresses components to determine a selection of the correct LOD map to use and intermediate texture addresses for pixels of the object between the perspectively correct addresses. The method first determines perspectively correct texture address values associated with four corners of a predefined span or grid of pixels. Then, a linear interpolation technique is implemented to calculate a rate of change of texture address components in the screen x and y directions for pixels between the perspectively bound span corners. This linear interpolation technique is performed in both screen directions to thereby create a potentially unique level of detail value for each pixel, which is then used as an index to select the correct pre-filtered LOD texture map. When mapping an individually determined LOD value per pixel, the effect of producing undesirable artifacts that may appear if a single LOD for an entire span or polygon is used, is obviated.
摘要翻译： 用于将纹理渲染到要在像素屏幕显示上显示的对象的方法和装置。 该技术利用透视正确的纹理地址之间的线性插值来计算各个纹理地址分量的变化率，以确定正确的LOD映射的使用选择，以及在透视正确的地址之间对象的像素的中间纹理地址。 该方法首先确定与预定义跨度或像素网格的四个角相关联的透视正确的纹理地址值。 然后，实现线性插值技术，以计算在透视边界角之间的像素的屏幕x和y方向上的纹理地址分量的变化率。 这种线性插值技术在两个屏幕方向上执行，从而为每个像素创建潜在唯一的细节值级，然后将其用作选择正确的预滤波LOD纹理图的索引。 当映射每个像素的单独确定的LOD值时，如果使用整个跨度或多边形的单个LOD，则可能出现产生不期望的伪影的效果。
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公开(公告)号：US06639598B2
公开(公告)日：2003-10-28
申请号：US09735037
申请日：2000-12-12
IPC分类号： G06T1700
CPC分类号： G06T15/04
摘要： Method and apparatus for rendering texture to an object to be displayed on a pixel screen display. This technique makes use of linear interpolation between perspectively correct texture address to calculate rates of change of individual texture addresses components to determine a selection of the correct LOD map to use and intermediate texture addresses for pixels of the object between the perspectively correct addresses. The method first determines perspectively correct texture address values associated with four corners of a predefined span or grid of pixels. Then, a linear interpolation technique is implemented to calculate a rate of change of texture address components in the screen x and y directions for pixels between the perspectively bound span corners. This linear interpolation technique is performed in both screen directions to thereby create a potentially unique level of detail value for each pixel, which is then used as an index to select the correct pre-filtered LOD texture map. When mapping an individually determined LOD value per pixel, the effect of producing undesirable artifacts that may appear if a single LOD for an entire span or polygon is used, is obviated.
摘要翻译： 用于将纹理渲染到要在像素屏幕显示上显示的对象的方法和装置。 该技术利用透视正确的纹理地址之间的线性内插来计算单个纹理地址分量的变化率，以确定正确的LOD图的使用选择，以及在透视正确的地址之间对象的像素的中间纹理地址。 该方法首先确定与预定义跨度或像素网格的四个角相关联的透视正确的纹理地址值。 然后，实现线性插值技术，以计算在透视边界角之间的像素的屏幕x和y方向上的纹理地址分量的变化率。 这种线性插值技术在两个屏幕方向上执行，从而为每个像素创建潜在唯一的细节值级，然后将其用作选择正确的预滤波LOD纹理图的索引。 当映射每个像素的单独确定的LOD值时，如果使用整个跨度或多边形的单个LOD，则可能出现产生不期望的伪影的效果。
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公开(公告)号：US06191793B1
公开(公告)日：2001-02-20
申请号：US09053591
申请日：1998-04-01
IPC分类号： G06T1140
CPC分类号： G06T15/04
摘要： A computationally efficient method for minimizing the visible effects of texture LOD transitions across a polygon. The minimization is accomplished by adding a dithering offset value to the LOD value computed for each pixel covered by a graphics primitive to produce a dithered pixel LOD value. The dithering offsets mat be generated from a table look-up based on the location of the pixel within a span of pixels. The dithered pixel LOD value is used to as an index in the selection of a single LOD texture map from which a textured pixel value is retrieved. The range of dithering offset values can be adjusted by modulating the values in the table look-up.
摘要翻译： 一种用于最小化跨多边形的纹理LOD转换的可见效果的计算有效的方法。 通过向由图形基元覆盖的每个像素计算的LOD值添加抖动偏移值以产生抖动像素LOD值来实现最小化。 基于像素跨度内的像素的位置，从表查找生成抖动偏移量。 抖动像素LOD值用于选择单个LOD纹理图的索引，从其中检索纹理像素值。 可以通过调整表查找中的值来调整抖动偏移值的范围。
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公开(公告)号：US08281183B2
公开(公告)日：2012-10-02
申请号：US12509803
申请日：2009-07-27
IPC分类号： G06F11/00
CPC分类号： G06F11/2028 , G06F11/2038 , G06F11/2048
摘要： An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry.
摘要翻译： 具有电路冗余的装置包括一组并行算术逻辑单元（ALU），冗余并行ALU，输入数据移位逻辑，其耦合到该组并行ALU并且可操作地耦合到冗余并行ALU。 输入数据移位逻辑将有缺陷的ALU的输入数据沿第一方向移动到该组中的相邻ALU。 当相邻的ALU是组中的最后一个或结束ALU时，移位逻辑继续将没有故障的结束ALU的输入数据移动到冗余并行ALU。 冗余的并行ALU然后对有缺陷的ALU进行操作。 输出数据移位逻辑耦合到并行冗余ALU和所有其他ALU输出的输出，以使输出数据在与输入移位逻辑相反的方向上相反的方向上移位，以重新输出用于继续处理的数据输出，包括用于存储或用于 由其他电路进一步处理。
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公开(公告)号：US06518974B2
公开(公告)日：2003-02-11
申请号：US09978973
申请日：2001-10-16
IPC分类号： G09G502
CPC分类号： G09G5/02 , G06F3/1431 , G09G5/12 , G09G5/393 , G09G5/395 , G09G2310/0229 , G09G2320/0261 , G09G2320/0276 , G09G2340/02 , G09G2340/0414 , G09G2340/0421 , G09G2340/125
摘要： In accordance with the present invention, the rate of change of texture addresses when mapped to individual pixels of a polygon is used to obtain the correct level of detail (LOD) map from a set of prefiltered maps. The method comprises a first determination of perspectively correct texture address values found at four corners of a predefined span or grid of pixels. Then, a linear interpolation technique is implemented to calculate a rate of change of texture addresses for pixels between the perspectively bound span corners. This linear interpolation technique is performed in both screen directions to thereby create a level of detail value for each pixel. The YUV formats described above have Y components for every pixel sample, and UN (they are also named Cr and Cb) components for every fourth sample. Every UN sample coincides with four (2×2) Y samples. This is identical to the organization of texels in U.S. Pat. No. 4,965,745 “YIQ-Based Color Cell Texturing”, incorporated herein by reference. The improvement of this algorithm is that a single 32-bit word contains four packed Y values, one value each for U and V, and optionally four one-bit Alpha components: YUV_0566: 5-bits each of four Y values, 6-bits each for U and V YUV_1544: 5-bits each of four Y values, 4-bits each for U and V, four 1-bit Alphas These components are converted from 4-, 5-, or 6-bit values to 8-bit values by the concept of color promotion. The reconstructed texels consist of Y components for every texel, and UN components repeated for every block of 2×2 texels. The combination of the YIQ-Based Color Cell Texturing concept, the packing of components into convenient 32-bit words, and color promoting the components to 8-bit values yields a compression from 96 bits down to 32 bits, or 3:1. There is a similarity between the trilinear filtering equation (performing bilinear filtering of four samples at each of two LODs, then linearly filtering those two results) and the motion compensation filtering equation (performing bilinear filtering of four samples from each of a “previous picture” and a “future picture”, then averaging those two results). Thus some of the texture filtering hardware can do double duty and perform the motion compensation filtering when those primitives are sent through the pipeline. The palette RAM area is conveniently used to store correction data (used to “correct” the predicted images that fall between the “I” images in an MPEG data stream) since, during motion compensation the texture palette memory would otherwise be unused.
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公开(公告)号：US07577869B2
公开(公告)日：2009-08-18
申请号：US11161672
申请日：2005-08-11
IPC分类号： G06F11/00
CPC分类号： G06F11/2028 , G06F11/2038 , G06F11/2048
摘要： An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry.
摘要翻译： 具有电路冗余的装置包括一组并行算术逻辑单元（ALU），冗余并行ALU，输入数据移位逻辑，其耦合到该组并行ALU并且可操作地耦合到冗余并行ALU。 输入数据移位逻辑将有缺陷的ALU的输入数据沿第一方向移动到该组中的相邻ALU。 当相邻的ALU是组中的最后一个或结束ALU时，移位逻辑继续将没有故障的结束ALU的输入数据移动到冗余并行ALU。 冗余的并行ALU然后对有缺陷的ALU进行操作。 输出数据移位逻辑耦合到并行冗余ALU和所有其他ALU输出的输出，以使输出数据在与输入移位逻辑相反的方向上相反的方向上移位，以重新输出用于继续处理的数据输出，包括用于存储或用于 由其他电路进一步处理。
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9.发明授权Geometric engine including a computational module for use in a video graphics controller 有权几何引擎包括用于视频图形控制器的计算模块公开(公告)号：US06630935B1
公开(公告)日：2003-10-07
申请号：US09556474
申请日：2000-04-21
IPC分类号： G06T1500
CPC分类号： G06T15/005 , G06F9/3851 , G06T1/20
摘要： A computation module and/or geometric engine for use in a video graphics processing circuit includes memory, a computation engine, a plurality of thread controllers, and an arbitration module. The computation engine is operably coupled to perform an operation based on an operation code and to provide a corresponding result to the memory as indicated by the operation code. Each of the plurality of thread controllers manages at least one corresponding thread of a plurality of threads. The plurality of threads constitutes an application. The arbitration module is coupled to the plurality of thread controllers and utilizes an application specific prioritization scheme to provide operation codes from the plurality of thread controllers to the computation engine such that idle time of the computation engine is minimized. The prioritization scheme prioritizes certain threads over other threads such that the throughput through the computation module is maximized.
摘要翻译： 用于视频图形处理电路的计算模块和/或几何引擎包括存储器，计算引擎，多个线程控制器和仲裁模块。 计算引擎可操作地耦合以执行基于操作代码的操作，并且向操作代码所指示的存储器提供相应的结果。 多个线程控制器中的每一个管理多个线程的至少一个对应的线程。 多个线程构成应用。 所述仲裁模块耦合到所述多个线程控制器，并且利用应用专用优先级方案来提供从所述多个线程控制器到所述计算引擎的操作代码，使得所述计算引擎的空闲时间被最小化。 优先排序方案将某些线程优先于其他线程，使得通过计算模块的吞吐量最大化。
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公开(公告)号：US20100017652A1
公开(公告)日：2010-01-21
申请号：US12509803
申请日：2009-07-27
IPC分类号： G06F11/20
CPC分类号： G06F11/2028 , G06F11/2038 , G06F11/2048
摘要： An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry.
摘要翻译： 具有电路冗余的装置包括一组并行算术逻辑单元（ALU），冗余并行ALU，输入数据移位逻辑，其耦合到该组并行ALU并且可操作地耦合到冗余并行ALU。 输入数据移位逻辑将有缺陷的ALU的输入数据沿第一方向移动到该组中的相邻ALU。 当相邻的ALU是组中的最后一个或结束ALU时，移位逻辑继续将没有故障的结束ALU的输入数据移动到冗余并行ALU。 冗余的并行ALU然后对有缺陷的ALU进行操作。 输出数据移位逻辑耦合到并行冗余ALU和所有其他ALU输出的输出，以使输出数据在与输入移位逻辑相反的方向上相反的方向上移位，以重新输出用于继续处理的数据输出，包括用于存储或用于 由其他电路进一步处理。
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