公开(公告)号：US08115512B1

公开(公告)日：2012-02-14

申请号：US12693643

申请日：2010-01-26

申请人： John G. O'Dwyer

发明人： John G. O'Dwyer

IPC分类号： H03K19/177 ,  H03K19/00

CPC分类号： H03M9/00

摘要： A method and apparatus for dynamically aligning high-speed signals in an integrated circuit are disclosed. For example, an integrated circuit according to one embodiment includes a logic fabric and at least one input/output interface coupled to the logic fabric. The input/output interface includes a plurality of input/output sites and an edge detector coupled to the plurality of input/output sites for detecting an edge in an input signal received by the integrated circuit. A plurality of delay lines are used to determine whether the input signal arrives too early or too late compared to a clock signal in the integrated circuit, and delays in the delay lines are adjusted to align the input signal with the clock signal in the integrated circuit.

摘要翻译： 公开了一种用于在集成电路中动态对准高速信号的方法和装置。 例如，根据一个实施例的集成电路包括逻辑结构和耦合到逻辑结构的至少一个输入/输出接口。 输入/输出接口包括多个输入/输出站点和耦合到多个输入/输出站点的边缘检测器，用于检测由集成电路接收的输入信号中的边沿。 使用多个延迟线来确定输入信号是否过早地与集成电路中的时钟信号相比过早，或者延迟线的延迟被调整以将输入信号与集成电路中的时钟信号对准 。

公开(公告)号：US08040153B1

公开(公告)日：2011-10-18

申请号：US12694169

申请日：2010-01-26

申请人： John G. O'Dwyer ,  Patrick J. Crotty

发明人： John G. O'Dwyer ,  Patrick J. Crotty

IPC分类号： H03K19/177

CPC分类号： H03M9/00

摘要： In one embodiment, a method and apparatus for configuring the internal memory cells of an integrated circuit through the logic fabric are disclosed. For example, an integrated circuit according to one embodiment includes a logic fabric and a plurality of input/output blocks coupled to the logic fabric, wherein the plurality of input/output blocks is positioned around the periphery of the logic fabric. The plurality of input/output blocks therefore forms a ring around the logic fabric, wherein a data path and a clock path are formed along the periphery of the logic fabric through the plurality of input/output blocks.

摘要翻译： 在一个实施例中，公开了一种用于通过逻辑结构配置集成电路的内部存储单元的方法和装置。 例如，根据一个实施例的集成电路包括逻辑结构和耦合到逻辑结构的多个输入/输出块，其中多个输入/输出块位于逻辑结构的外围周围。 因此，多个输入/输出块在逻辑结构周围形成环，其中通过多个输入/输出块沿着逻辑结构的外围形成数据路径和时钟路径。

公开(公告)号：US07728642B1

公开(公告)日：2010-06-01

申请号：US12270102

申请日：2008-11-13

申请人： John G. O'Dwyer

发明人： John G. O'Dwyer

IPC分类号： H03H11/26

CPC分类号： H03K5/135 ,  H03K2005/00247

摘要： A programmable delay line includes a first oscillator that is enabled and generates a plurality of clock cycles of a clock signal in response to a transition of the input signal. A first programmable ripple counter is coupled to the first oscillator, counts with each successive clock cycle to a programmed count, and generates a first signal in response to reaching the programmed count. A control circuit is coupled to the first oscillator and to the first programmable ripple counter. The control circuit transitions the output signal and disables the first oscillator in response to the first signal.

摘要翻译： 可编程延迟线包括响应于输入信号的转变而被使能并产生时钟信号的多个时钟周期的第一振荡器。 第一可编程纹波计数器耦合到第一振荡器，以每个连续的时钟周期计数到编程的计数，并且响应于达到编程的计数而产生第一信号。 控制电路耦合到第一振荡器和第一可编程纹波计数器。 控制电路转换输出信号，并响应于第一信号禁用第一振荡器。

公开(公告)号：US08890571B1

公开(公告)日：2014-11-18

申请号：US13347279

申请日：2012-01-10

申请人： John G. O'Dwyer

发明人： John G. O'Dwyer

IPC分类号： H03K19/00 ,  H03L7/06

CPC分类号： H03M9/00

摘要： A method and apparatus for aligning an input signal to a clock signal in an integrated circuit are disclosed. The method includes receiving an input signal; determining whether the input signal is arriving too early or too late via a plurality of delay lines; and adjusting a delay of the plurality of delay lines in accordance with a result of the determining.

摘要翻译： 公开了一种用于将输入信号与集成电路中的时钟信号对准的方法和装置。 该方法包括接收输入信号; 通过多个延迟线确定所述输入信号是否到达太早或太迟; 以及根据所述确定的结果调整所述多个延迟线的延迟。

公开(公告)号：US08134878B1

公开(公告)日：2012-03-13

申请号：US12695099

申请日：2010-01-27

申请人： Schuyler E. Shimanek ,  Mikhail A. Wolf ,  Sanford L. Helton ,  John G. O'Dwyer

发明人： Schuyler E. Shimanek ,  Mikhail A. Wolf ,  Sanford L. Helton ,  John G. O'Dwyer

IPC分类号： G11C7/00

CPC分类号： H03K19/1776 ,  H03K19/17736 ,  H03K19/1774

摘要： A method of calibrating memory controller signals within an integrated circuit (IC) can include determining an internal delay of a clock network of the IC and generating a calibrated clock signal by applying a first delay to an uncalibrated clock signal, wherein the first delay is determined by subtracting the internal delay of the clock network of the IC from a bitperiod of the uncalibrated clock signal. The method can include determining a classification of at least one data signal according to timing of positive and negative edges of the at least one data signal in comparison with edges of the calibrated clock signal and aligning at least one of positive or negative edges of the at least one data signal to occur at midpoints between edges of the calibrated clock signal according to the classification of the at least one data signal.

摘要翻译： 校准集成电路（IC）内的存储器控​​制器信号的方法可以包括：确定IC的时钟网络的内部延迟并通过向未校准的时钟信号施加第一延迟并产生校准时钟信号，其中确定第一延迟 通过从未校准的时钟信号的比特周减去IC的时钟网络的内部延迟。 该方法可以包括根据校准的时钟信号的边缘与至少一个数据信号的正边缘和负边缘的定时相对应地确定至少一个数据信号的分类，并且对准至少一个数据信号的正或负边缘 至少一个数据信号根据至少一个数据信号的分类在校准时钟信号的边缘之间的中点发生。

公开(公告)号：US08013764B1

公开(公告)日：2011-09-06

申请号：US12693648

申请日：2010-01-26

申请人： John G. O'Dwyer

发明人： John G. O'Dwyer

IPC分类号： H03M9/00

CPC分类号： H03M9/00

摘要： In one embodiment, a method and apparatus for shifting the bits of a data word are disclosed. For example, a deserializer according to one embodiment includes an input register bank for capturing serial data comprising n bits, an intermediate register bank, and a strobe mux coupled to an input of the intermediate register bank. An input of the intermediate register bank is coupled to an output of the input register bank. The strobe mux comprises a single multiplexer configured to select a bitslip strobe signal that controls an order in which the n bits of the serial data are captured in the intermediate register bank.

摘要翻译： 在一个实施例中，公开了一种用于移位数据字的位的方法和装置。 例如，根据一个实施例的解串器包括用于捕获包括n位的串行数据的输入寄存器组，中间寄存器组和耦合到中间寄存器组的输入的选通复用器。 中间寄存器组的输入耦合到输入寄存器组的输出端。 选通复用器包括单个多路复用器，其被配置为选择位片选通信号，其控制在中间寄存器组中捕获串行数据的n位的顺序。

公开(公告)号：US07521987B1

公开(公告)日：2009-04-21

申请号：US11999192

申请日：2007-12-03

申请人： Edward Cullen ,  John G. O'Dwyer ,  Jinsong Huang

发明人： Edward Cullen ,  John G. O'Dwyer ,  Jinsong Huang

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  H03K19/17744 ,  H03K19/17788

摘要： Multiple supply voltage select circuit for use with reduced supply voltage levels and method for using same are described. A first and second set of P-channel transistors are used for voltage pull-up at a common node using two supply voltages, respectively. A P-channel transistor from each of the sets is gated by output of a respective level shifter. Both of the level shifters are biased with a higher of the two supply voltages. First and second inputs are respectively provided to the level shifters and to gates of other P-channel transistors of each of the sets.

摘要翻译： 描述了用于降低电源电压电平的多电源电压选择电路及其使用方法。 第一和第二组P沟道晶体管分别用于使用两个电源电压的公共节点处的电压上拉。 来自每个组的P沟道晶体管由相应电平移位器的输出选通。 两个电平移位器都被两个电源电压中较高的一个偏置。 第一和第二输入分别提供给电平移位器和每组的其它P沟道晶体管的栅极。

公开(公告)号：US07225099B1

公开(公告)日：2007-05-29

申请号：US11055213

申请日：2005-02-10

申请人： John G. O'Dwyer

发明人： John G. O'Dwyer

IPC分类号： G01K7/01

CPC分类号： G01K7/01

摘要： Temperature measurement of an integrated circuit may be made using a bandgap voltage reference. In one example, a circuit includes a bandgap reference, a first output terminal, a second output terminal, and a calculation circuit. The bandgap reference includes a first amplifier having a first amplifier input coupled to a first transistor and a second amplifier input coupled to a second transistor. The first output terminal is coupled to the first and second transistors and is operable to provide a temperature independent voltage. The second output terminal is operable to provide a temperature dependent voltage. The calculation circuit is coupled to the first output terminal and the second output terminal and is configured to subtract from the temperature dependent voltage a difference between the temperature independent voltage and a nominal temperature independent voltage.

摘要翻译： 可以使用带隙电压参考来进行集成电路的温度测量。 在一个示例中，电路包括带隙基准，第一输出端，​​第二输出端和计算电路。 带隙基准包括具有耦合到第一晶体管的第一放大器输入和耦合到第二晶体管的第二放大器输入的第一放大器。 第一输出端耦合到第一和第二晶体管，并且可操作以提供与温度无关的电压。 第二输出端子可操作以提供与温度有关的电压。 计算电路耦合到第一输出端和第二输出端，并被配置为从温度相关电压中减去独立于温度的电压与标称温度独立电压之间的差值。