公开(公告)号：US07407863B2

公开(公告)日：2008-08-05

申请号：US10680509

申请日：2003-10-07

申请人： Kuang Chien Hsieh ,  Keh-Yung Cheng ,  Kuo-Lih Chang ,  John H. Epple ,  Gregory Pickrell

发明人： Kuang Chien Hsieh ,  Keh-Yung Cheng ,  Kuo-Lih Chang ,  John H. Epple ,  Gregory Pickrell

IPC分类号： H01L21/76

CPC分类号： H01L21/02392 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02546 ,  H01L21/02631 ,  H01L21/187

摘要： Amorphous and polycrystalline III-V semiconductor including (Ga,As), (Al,As), (In,As), (Ga,N), and (Ga,P) materials were grown at low temperatures on semiconductor substrates. After growth, different substrates containing the low temperature grown material were pressed together in a pressure jig before being annealed. The annealing temperatures ranged from about 300° C. to 800° C. for annealing times between 30 minutes and 10 hours, depending on the bonding materials. The structures remained pressed together throughout the course of the annealing. Strong bonds were obtained for bonding layers between different substrates that were as thin as 3 nm and as thick as 600 nm. The bonds were ohmic with a relatively small resistance, optically transparent, and independent of the orientation of the underlying structures.

摘要翻译： 包括（Ga，As），（Al，As），（In，As），（Ga，N）和（Ga，P）材料的非晶和多晶III-V半导体在低温下生长在半导体衬底上。 生长后，将含有低温生长材料的不同基材在退火之前在压力夹具中压在一起。 取决于粘合材料，退火温度范围为约300℃至800℃，退火时间为30分钟至10小时。 在整个退火过程中，结构保持压在一起。 获得了很强的键，用于在不同基底之间的结合层，其厚度为3nm，厚度为600nm。 这些键是欧姆的，具有相对小的电阻，光学透明并且独立于下面的结构的取向。

公开(公告)号：US20140264679A1

公开(公告)日：2014-09-18

申请号：US13994716

申请日：2013-03-15

申请人： Kevin J. Lee ,  Tahir Ghani ,  Joseph M. Steigerwald ,  John H. Epple ,  Yih Wang

发明人： Kevin J. Lee ,  Tahir Ghani ,  Joseph M. Steigerwald ,  John H. Epple ,  Yih Wang

IPC分类号： H01L43/02 ,  H01L43/12

CPC分类号： H01L43/12 ,  G11C11/161 ,  H01L27/222 ,  H01L27/226 ,  H01L43/08

摘要： An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) with an upper MTJ layer, lower MTJ layer, and tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. In an embodiment the first and second ILDs directly contact one another. Other embodiments are described herein.

摘要翻译： 实施例将逻辑芯片内的诸如自旋转矩传递磁阻随机存取存储器（STT-MRAM）的存储器集成。 STT-MRAM包括具有上部MTJ层，较低MTJ层和直接接触上层MTJ层和下层MTJ层的隧道势垒的磁隧道结（MTJ）; 其中上MTJ层包括上MTJ层侧壁，下MTJ层包括水平地偏离上MTJ层的下MTJ侧壁。 另一个实施例包括包含MTJ的存储区域和位于衬底上的逻辑区域; 其中水平面与MTJ相邻，邻近MTJ的第一层间电介质（ILD）材料和包含在逻辑区域中的第二ILD材料，第一和第二ILD材料彼此不相等。 在一个实施例中，第一和第二ILD直接彼此接触。 本文描述了其它实施例。

公开(公告)号：US20140264668A1

公开(公告)日：2014-09-18

申请号：US13994715

申请日：2013-03-15

申请人： Kevin J. Lee ,  Tahir Ghani ,  Joseph M. Steigerwald ,  John H. Epple ,  Yih Wang

发明人： Kevin J. Lee ,  Tahir Ghani ,  Joseph M. Steigerwald ,  John H. Epple ,  Yih Wang

IPC分类号： H01L43/02 ,  H01L43/12

CPC分类号： H01L27/222 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

摘要： An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.

摘要翻译： 实施例将逻辑芯片内的诸如自旋转矩传递磁阻随机存取存储器（STT-MRAM）的存储器集成。 STT-MRAM包括具有上MTJ层，下MTJ层和直接接触上MTJ层和下MTJ层的隧道势垒的磁隧道结（MTJ）; 其中上MTJ层包括上MTJ层侧壁，下MTJ层包括水平地偏离上MTJ层的下MTJ侧壁。 另一个实施例包括包含MTJ的存储区域和位于衬底上的逻辑区域; 其中水平面与MTJ相邻，邻近MTJ的第一层间电介质（ILD）材料和包含在逻辑区域中的第二ILD材料，第一和第二ILD材料彼此不相等。 本文描述了其它实施例。

公开(公告)号：US20080296619A1

公开(公告)日：2008-12-04

申请号：US12138167

申请日：2008-06-12

申请人： Kuang Chien Hsieh ,  Keh-Yung Cheng ,  Kuo-Lih Chang ,  John H. Epple ,  Gregory Pickrell

发明人： Kuang Chien Hsieh ,  Keh-Yung Cheng ,  Kuo-Lih Chang ,  John H. Epple ,  Gregory Pickrell

IPC分类号： H01L29/20 ,  H01L21/30

CPC分类号： H01L21/02392 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02546 ,  H01L21/02631 ,  H01L21/187

摘要： Amorphous and polycrystalline III-V semiconductor including (Ga,As), (Al,As), (In,As), (Ga,N), and (Ga,P) materials were grown at low temperatures on semiconductor substrates. After growth, different substrates containing the low temperature grown material were pressed together in a pressure jig before being annealed. The annealing temperatures ranged from about 300° C. to 800° C. for annealing times between 30 minutes and 10 hours, depending on the bonding materials. The structures remained pressed together throughout the course of the annealing. Strong bonds were obtained for bonding layers between different substrates that were as thin as 3 nm and as thick as 600 nm. The bonds were ohmic with a relatively small resistance, optically transparent, and independent of the orientation of the underlying structures.

摘要翻译： 包括（Ga，As），（Al，As），（In，As），（Ga，N）和（Ga，P）材料的非晶和多晶III-V半导体在低温下生长在半导体衬底上。 生长后，将含有低温生长材料的不同基材在退火之前在压力夹具中压在一起。 取决于粘合材料，退火温度范围为约300℃至800℃，退火时间为30分钟至10小时。 在整个退火过程中，结构保持压在一起。 获得了很强的键，用于在不同基底之间的结合层，其厚度为3nm，厚度为600nm。 这些键是欧姆的，具有相对小的电阻，光学透明并且独立于下面的结构的取向。