公开(公告)号：US07407863B2

公开(公告)日：2008-08-05

申请号：US10680509

申请日：2003-10-07

申请人： Kuang Chien Hsieh ,  Keh-Yung Cheng ,  Kuo-Lih Chang ,  John H. Epple ,  Gregory Pickrell

发明人： Kuang Chien Hsieh ,  Keh-Yung Cheng ,  Kuo-Lih Chang ,  John H. Epple ,  Gregory Pickrell

IPC分类号： H01L21/76

CPC分类号： H01L21/02392 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02546 ,  H01L21/02631 ,  H01L21/187

摘要： Amorphous and polycrystalline III-V semiconductor including (Ga,As), (Al,As), (In,As), (Ga,N), and (Ga,P) materials were grown at low temperatures on semiconductor substrates. After growth, different substrates containing the low temperature grown material were pressed together in a pressure jig before being annealed. The annealing temperatures ranged from about 300° C. to 800° C. for annealing times between 30 minutes and 10 hours, depending on the bonding materials. The structures remained pressed together throughout the course of the annealing. Strong bonds were obtained for bonding layers between different substrates that were as thin as 3 nm and as thick as 600 nm. The bonds were ohmic with a relatively small resistance, optically transparent, and independent of the orientation of the underlying structures.

摘要翻译： 包括（Ga，As），（Al，As），（In，As），（Ga，N）和（Ga，P）材料的非晶和多晶III-V半导体在低温下生长在半导体衬底上。 生长后，将含有低温生长材料的不同基材在退火之前在压力夹具中压在一起。 取决于粘合材料，退火温度范围为约300℃至800℃，退火时间为30分钟至10小时。 在整个退火过程中，结构保持压在一起。 获得了很强的键，用于在不同基底之间的结合层，其厚度为3nm，厚度为600nm。 这些键是欧姆的，具有相对小的电阻，光学透明并且独立于下面的结构的取向。

公开(公告)号：US07535944B1

公开(公告)日：2009-05-19

申请号：US10860607

申请日：2004-06-03

申请人： Peter Guilfoyle ,  Jongwoo Kim ,  Duane A. Loudeback ,  Gregory Pickrell

发明人： Peter Guilfoyle ,  Jongwoo Kim ,  Duane A. Loudeback ,  Gregory Pickrell

IPC分类号： H01S5/00

CPC分类号： H01S5/423 ,  G02B6/4214 ,  H01S5/0422 ,  H01S5/1032 ,  H01S5/105 ,  H01S5/141 ,  H01S5/18308 ,  H01S5/18311 ,  H01S5/187 ,  H01S5/2063 ,  H01S5/4012

摘要： An optical coupler comprises first and second mirrors. The first mirror is positioned with respect to the second mirror so that a resonant cavity is defined between them. A waveguide structure is positioned in the resonant cavity and includes a photonic crystal coupler. A thickness of the resonant cavity is selected so that a phase matching condition is satisfied for resonance in the resonant cavity. At least one of the first and second mirrors may be formed from a structure in an optoelectronic device. Alternatively, at least one of the first and second mirrors is formed from a semiconductor layer. At least one of the first and second mirrors may be formed as a semiconductor distributed bragg reflector, or as a dielectric distributed bragg reflector. At least one of the first and second mirrors may be a mirror in a vertical cavity surface emitting laser (VCSEL) structure. The photonic crystal coupler structure may be shaped so that first order modes of light incident upon the photonic crystal coupler structure are coupled into the waveguide while zero-order modes are reflected out into the resonant cavity and reflected by the mirror.

摘要翻译： 光耦合器包括第一和第二反射镜。 第一镜相对于第二镜定位，使得在它们之间限定谐振腔。 波导结构位于谐振腔中并且包括光子晶体耦合器。 选择谐振腔的厚度，使得谐振腔中的谐振满足相位匹配条件。 第一和第二反射镜中的至少一个可以由光电器件中的结构形成。 或者，第一和第二反射镜中的至少一个由半导体层形成。 第一和第二反射镜中的至少一个可以形成为半导体分布式布拉格反射器，或者形成为电介质分布布拉格反射器。 第一和第二反射镜中的至少一个可以是垂直腔表面发射激光（VCSEL）结构中的反射镜。 光子晶体耦合器结构可以被成形为使得入射到光子晶体耦合器结构的一阶光模耦合到波导中，而零阶模式被反射到谐振腔并被反射镜反射。

公开(公告)号：US20080296619A1

公开(公告)日：2008-12-04

申请号：US12138167

申请日：2008-06-12

申请人： Kuang Chien Hsieh ,  Keh-Yung Cheng ,  Kuo-Lih Chang ,  John H. Epple ,  Gregory Pickrell

发明人： Kuang Chien Hsieh ,  Keh-Yung Cheng ,  Kuo-Lih Chang ,  John H. Epple ,  Gregory Pickrell

IPC分类号： H01L29/20 ,  H01L21/30

CPC分类号： H01L21/02392 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02546 ,  H01L21/02631 ,  H01L21/187

摘要： Amorphous and polycrystalline III-V semiconductor including (Ga,As), (Al,As), (In,As), (Ga,N), and (Ga,P) materials were grown at low temperatures on semiconductor substrates. After growth, different substrates containing the low temperature grown material were pressed together in a pressure jig before being annealed. The annealing temperatures ranged from about 300° C. to 800° C. for annealing times between 30 minutes and 10 hours, depending on the bonding materials. The structures remained pressed together throughout the course of the annealing. Strong bonds were obtained for bonding layers between different substrates that were as thin as 3 nm and as thick as 600 nm. The bonds were ohmic with a relatively small resistance, optically transparent, and independent of the orientation of the underlying structures.

摘要翻译： 包括（Ga，As），（Al，As），（In，As），（Ga，N）和（Ga，P）材料的非晶和多晶III-V半导体在低温下生长在半导体衬底上。 生长后，将含有低温生长材料的不同基材在退火之前在压力夹具中压在一起。 取决于粘合材料，退火温度范围为约300℃至800℃，退火时间为30分钟至10小时。 在整个退火过程中，结构保持压在一起。 获得了很强的键，用于在不同基底之间的结合层，其厚度为3nm，厚度为600nm。 这些键是欧姆的，具有相对小的电阻，光学透明并且独立于下面的结构的取向。

公开(公告)号：US20050074927A1

公开(公告)日：2005-04-07

申请号：US10680509

申请日：2003-10-07

申请人： Kuang Hsieh ,  Keh-Yung Cheng ,  Kuo-Lih Chang ,  John Epple ,  Gregory Pickrell

发明人： Kuang Hsieh ,  Keh-Yung Cheng ,  Kuo-Lih Chang ,  John Epple ,  Gregory Pickrell

IPC分类号： H01L21/18 ,  H01L21/20 ,  H01L21/203 ,  H01L21/324 ,  H01L33/00 ,  H01L21/335

CPC分类号： H01L21/02392 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02546 ,  H01L21/02631 ,  H01L21/187

摘要： Amorphous and polycrystalline III-V semiconductor including (Ga,As), (Al,As), (In,As), (Ga,N), and (Ga,P) materials were grown at low temperatures on semiconductor substrates. After growth, different substrates containing the low temperature grown material were pressed together in a pressure jig before being annealed. The annealing temperatures ranged from about 300° C. to 800° C. for annealing times between 30 minutes and 10 hours, depending on the bonding materials. The structures remained pressed together throughout the course of the annealing. Strong bonds were obtained for bonding layers between different substrates that were as thin as 3 nm and as thick as 600 nm. The bonds were ohmic with a relatively small resistance, optically transparent, and independent of the orientation of the underlying structures.

摘要翻译： 包括（Ga，As），（Al，As），（In，As），（Ga，N）和（Ga，P）材料的非晶和多晶III-V半导体在低温下生长在半导体衬底上。 生长后，将含有低温生长材料的不同基材在退火之前在压力夹具中压在一起。 取决于粘合材料，退火温度范围为约300℃至800℃，退火时间为30分钟至10小时。 在整个退火过程中，结构保持压在一起。 获得了很强的键，用于在不同基底之间的结合层，其厚度为3nm，厚度为600nm。 这些键是欧姆的，具有相对小的电阻，光学透明并且独立于下面的结构的取向。

公开(公告)号：US07767480B1

公开(公告)日：2010-08-03

申请号：US11063230

申请日：2005-02-22

申请人： Gregory Pickrell ,  Duane A. Louderback ,  Peter Guilfoyle

发明人： Gregory Pickrell ,  Duane A. Louderback ,  Peter Guilfoyle

IPC分类号： H01L21/00

CPC分类号： H01S5/18344 ,  C30B23/02 ,  C30B29/40 ,  C30B29/42 ,  H01S2304/02

摘要： A method of manufacturing a distributed Bragg reflector (DBR) in group III-V semiconductor compounds with improved optical and electrical characteristics is provided. A selected DBR structure is achieved by sequential exposure of a substrate to predetermined combinations of the elemental sources to produce a pair of DBR layers of compound alloys and a graded region including one or more discrete additional layers between the DBR layers of intermediate alloy composition. Exposure durations and combinations of the elemental sources in each exposure are predetermined by DBR design characteristics.

摘要翻译： 提供了一种在具有改进的光学和电学特性的III-V族半导体化合物中制造分布式布拉格反射体（DBR）的方法。 选择的DBR结构通过将衬底顺序地暴露于元素源的预定组合来实现，以产生一对复合合金的DBR层，以及在中间合金组成的DBR层之间包括一个或多个离散的附加层的分级区域。 每次曝光中的曝光持续时间和元素源的组合由DBR设计特征预先确定。