公开(公告)号：US11788202B2

公开(公告)日：2023-10-17

申请号：US18046943

申请日：2022-10-17

申请人： Government of the United States, as represented by the Secretary of the Air Force

发明人： Vladimir Tassev

IPC分类号： C30B25/04 ,  H01L21/02 ,  C30B29/44 ,  C30B29/40 ,  C30B25/18 ,  G02F1/355 ,  C30B29/42 ,  C30B29/48 ,  C30B25/02 ,  H01L31/18

CPC分类号： C30B25/04 ,  C30B25/02 ,  C30B25/18 ,  C30B29/403 ,  C30B29/406 ,  C30B29/42 ,  C30B29/44 ,  C30B29/48 ,  G02F1/3556 ,  H01L21/024 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02293 ,  H01L21/02387 ,  H01L21/02389 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/02398 ,  H01L21/02458 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02505 ,  H01L21/02538 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02551 ,  H01L21/02568 ,  H01L21/02658 ,  H01L31/1828 ,  G02F1/3558

摘要： A method of performing HVPE heteroepitaxy comprises exposing a substrate to a carrier gas, a first precursor gas, a Group II/III element, and ternary-forming gasses (V/VI group precursor), to form a heteroepitaxial growth of a binary, ternary, and/or quaternary compound on the substrate; wherein the carrier gas is Hz, wherein the first precursor gas is HCl, the Group II/III element comprises at least one of Zn, Cd, Hg, Al, Ga, and In; and wherein the ternary-forming gasses comprise at least two or more of AsH3 (arsine), PH3 (phosphine), H2Se (hydrogen selenide), HzTe (hydrogen telluride), SbH3 (hydrogen antimonide, or antimony tri-hydride, or stibine), H2S (hydrogen sulfide), NH3 (ammonia), and HF (hydrogen fluoride); flowing the carrier gas over the Group II/III element; exposing the substrate to the ternary-forming gasses in a predetermined ratio of first ternary-forming gas to second ternary-forming gas (1tf:2tf ratio); and changing the 1tf:2tf ratio over time.

公开(公告)号：US10070820B2

公开(公告)日：2018-09-11

申请号：US14265234

申请日：2014-04-29

申请人： Micro Nipple Technology Co., Ltd.

发明人： Juang-Tang Huang

IPC分类号： A61B5/00 ,  A61B5/15 ,  A61B5/05 ,  A61B5/145

CPC分类号： H01L31/035236 ,  A61B5/05 ,  A61B5/14514 ,  A61B5/14532 ,  A61B5/14546 ,  A61B5/150022 ,  A61B5/150282 ,  A61B5/150969 ,  A61B5/150984 ,  A61B5/6833 ,  A61B5/6849 ,  A61B5/685 ,  A61B2562/046 ,  A61B2562/125 ,  H01L21/02392 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02507 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/0262 ,  H01L31/03046 ,  H01L31/105 ,  H01L31/1844 ,  Y02E10/544 ,  Y02P70/521

摘要： Transdermal microneedles continuous monitoring system is provided. The continuous system monitoring includes a substrate, a microneedle unit, a signal processing unit and a power supply unit. The microneedle unit at least comprises a first microneedle set used as a working electrode and a second microneedle set used as a reference electrode, the first and second microneedle sets arranging on the substrate. Each microneedle set comprises at least a microneedle. The first microneedle set comprises at least a sheet having a through hole on which a barbule forms at the edge. One of the sheets provides the through hole from which the barbules at the edge of the other sheets go through, and the barbules are disposed separately.

公开(公告)号：US20170179046A1

公开(公告)日：2017-06-22

申请号：US15449993

申请日：2017-03-05

申请人： Invensas Corporation

发明人： Liang Wang ,  Ilyas Mohammed ,  Masud Beroz

IPC分类号： H01L23/00 ,  H01L23/544 ,  H01L21/02

CPC分类号： H01L23/562 ,  H01L21/02002 ,  H01L21/02035 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/02414 ,  H01L21/6835 ,  H01L23/544 ,  H01L24/19 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L27/0207 ,  H01L33/005 ,  H01L33/0062 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/351 ,  H01L2924/00

摘要： In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates.

公开(公告)号：US09627482B2

公开(公告)日：2017-04-18

申请号：US15092724

申请日：2016-04-07

申请人： International Business Machines Corporation

发明人： Cheng-Wei Cheng ,  Pranita Kerber ,  Young-Hee Kim ,  Effendi Leobandung ,  Yanning Sun

IPC分类号： H01L29/10 ,  H01L29/205 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/207 ,  H01L29/06 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/8252 ,  H01L29/08

CPC分类号： H01L29/20 ,  H01L21/02392 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/0257 ,  H01L21/30612 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/8252 ,  H01L29/0603 ,  H01L29/0607 ,  H01L29/0657 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1041 ,  H01L29/1054 ,  H01L29/12 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833

摘要： A method for fabricating a semiconductor device may include receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed thereon, over-etching the channel layer to expose an extension region below the gate structure, epitaxially growing a halo layer on the exposed extension region using a first in-situ dopant and epitaxially growing a source or drain on the halo layer using a second in-situ dopant, wherein the first in-situ dopant and the second in-situ dopant are of opposite doping polarity. Using an opposite doping polarity may provide an energy band barrier for the semiconductor device and reduce leakage current. A corresponding apparatus is also disclosed herein.

公开(公告)号：US09419110B2

公开(公告)日：2016-08-16

申请号：US14938169

申请日：2015-11-11

申请人： IMEC VZW

发明人： Clement Merckling ,  Nadine Collaert

IPC分类号： H01L21/20 ,  H01L29/66 ,  H01L29/20 ,  H01L29/417 ,  H01L29/78 ,  H01L21/02

CPC分类号： H01L29/66795 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/0243 ,  H01L21/02455 ,  H01L21/02513 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02658 ,  H01L21/02661 ,  H01L21/76224 ,  H01L29/20 ,  H01L29/41725 ,  H01L29/7848

摘要： A method for growing a III-V semiconductor structure on a SinGe1-n substrate, wherein n is from 0 to 1 is provided. The method includes the steps of: (a) bringing a SinGe1-n substrate to a high temperature; (b) exposing the area to a group V precursor in a carrier gas for from 5 to 30 min, thereby forming a doped region at said area; (c) bringing the SinGe1-n substrate to a low temperature; (d) exposing the doped region to a group III precursor in a carrier gas and to a group V precursor in a carrier gas until a nucleation layer of III-V material of from 5 to 15 nm is formed on the nucleation layer; (e) bringing the SinGe1-n substrate to an intermediate temperature; and (f) exposing the nucleation layer to a group III precursor in a carrier gas and to a group V precursor in a carrier gas.

摘要翻译： 提供了一种在SinGe1-n衬底上生长III-V半导体结构的方法，其中n为0至1。 该方法包括以下步骤：（a）使SinGe1-n衬底达到高温; （b）将载体气体中的V族前体暴露于5〜30分钟，由此在该区域形成掺杂区域; （c）使SinGe1-n基板处于低温; （d）将载体气体中的掺杂区域暴露于III族前体，并在载气中暴露于V族前体，直至在成核层上形成5〜15nm的III-V材料的成核层; （e）使SinGe1-n基板达到中间温度; 和（f）将成核层暴露于载气中的III族前体和载气中的V族前体。

公开(公告)号：US09318327B2

公开(公告)日：2016-04-19

申请号：US11563712

申请日：2006-11-28

申请人： Michael John Bergmann ,  Jason Hansen ,  David Todd Emerson ,  Kevin Ward Haberern

发明人： Michael John Bergmann ,  Jason Hansen ,  David Todd Emerson ,  Kevin Ward Haberern

IPC分类号： H01L29/06 ,  H01L21/02 ,  H01L31/0236 ,  H01L33/00

CPC分类号： H01L21/02658 ,  H01L21/02378 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/02403 ,  H01L21/0242 ,  H01L21/02425 ,  H01L21/0254 ,  H01L31/0236 ,  H01L31/02363 ,  H01L33/007 ,  Y02E10/50

摘要： Semiconductor device structures are provided that are suitable for use in the fabrication of electronic devices such as light emitting diodes. The semiconductor device structures include a substrate having a roughened growth surface suitable for supporting the growth of an epitaxial region thereon. The device structure can include an epitaxial region having reduced defects and/or improved radiation extraction efficiency on the roughened growth surface of the substrate. The roughened growth surface of the substrate can have an average roughness Ra of at least about 1 nanometer (nm) and an average peak to valley height Rz of at least about 10 nanometers (nm).

摘要翻译： 提供了适用于制造诸如发光二极管的电子设备的半导体器件结构。 半导体器件结构包括具有适于支持其上的外延区域的生长的粗糙生长表面的衬底。 器件结构可以包括在衬底的粗糙化生长表面上具有减小的缺陷和/或改进的辐射提取效率的外延区域。 基底的粗糙化的生长表面可以具有至少约1纳米（nm）的平均粗糙度Ra和至少约10纳米（nm）的平均峰谷高度Rz。

公开(公告)号：US20150214307A1

公开(公告)日：2015-07-30

申请号：US14507884

申请日：2014-10-07

申请人： Mitsubishi Electric Corporation

发明人： Harunaka Yamaguchi

IPC分类号： H01L29/201 ,  H01L31/107 ,  H01L31/0304 ,  H01L21/306 ,  H01L29/207 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L31/18 ,  H01S5/343

CPC分类号： H01L21/30604 ,  H01L21/02392 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/02546 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/30621 ,  H01L29/207 ,  H01L29/7785 ,  H01L31/03042 ,  H01L31/03046 ,  H01L31/1075 ,  H01L31/1844 ,  H01S5/305 ,  H01S5/309 ,  H01S5/3407 ,  H01S5/34306 ,  Y02E10/544

摘要： A method for manufacturing a semiconductor device includes: forming a buffer layer on a substrate; and sequentially forming an undoped multiplication layer, an electric field alleviating layer, a light absorption layer, and a window layer on the buffer layer, in that order, for forming an avalanche photodiode. Carbon is incorporated into the electric field alleviating layer as a p-type dopant, and a dopant impurity producing n-type conductivity and carbon are incorporated into the buffer layer.

摘要翻译： 一种制造半导体器件的方法包括：在衬底上形成缓冲层; 并依次形成缓冲层上的未掺杂倍增层，电场缓和层，光吸收层和窗口层，以形成雪崩光电二极管。 将碳作为p型掺杂剂并入电场缓和层中，并且将产生n型导电性的掺杂剂杂质和碳并入缓冲层。

公开(公告)号：US09031111B2

公开(公告)日：2015-05-12

申请号：US14310490

申请日：2014-06-20

申请人： Sumitomo Electric Device Innovations, Inc.

发明人： Tatsuya Takeuchi ,  Taro Hasegawa

IPC分类号： H01S5/00 ,  H01S5/20 ,  H01S5/22 ,  H01S5/227 ,  H01S5/30 ,  H01L21/02

CPC分类号： H01S5/20 ,  H01L21/02392 ,  H01L21/02461 ,  H01L21/02543 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02581 ,  H01S5/2227 ,  H01S5/2275 ,  H01S5/3013

摘要： A method of manufacturing an optical semiconductor device including: forming a mesa structure including a first conductivity type cladding layer, an active layer and a second conductivity type cladding layer in this order on a first conductivity type semiconductor substrate, an upper most surface of the mesa structure being constituted of an upper face of the second conductivity type cladding layer; growing a first burying layer burying both sides of the mesa structure at higher position than the active layer; forming an depressed face by etching both edges of the upper face of the second conductivity type cladding layer; and growing a second burying layer of the first conductivity type on the depressed face of the second conductivity type cladding layer and the first burying layer.

摘要翻译： 一种制造光半导体器件的方法，包括：在第一导电型半导体衬底上形成包括第一导电型包覆层，有源层和第二导电型包覆层的台面结构，台面的最上表面 结构由第二导电型包层的上表面构成; 生长的第一个埋藏层在比活性层更高的位置掩埋台面结构的两侧; 通过蚀刻第二导电型包覆层的上表面的两个边缘来形成凹陷面; 以及在所述第二导电型包覆层和所述第一掩埋层的凹面上生长所述第一导电类型的第二掩埋层。

公开(公告)号：US20150001466A1

公开(公告)日：2015-01-01

申请号：US14490128

申请日：2014-09-18

申请人： Sumitomo Electric Industries, Ltd.

发明人： Katsushi Akita ,  Takashi Ishizuka ,  Kei Fujii ,  Youichi Nagai

IPC分类号： H01L31/0352 ,  H01L31/0304

CPC分类号： H01L31/035209 ,  H01L21/02392 ,  H01L21/02458 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02507 ,  H01L21/02546 ,  H01L31/03042 ,  H01L31/03046 ,  H01L31/035236 ,  H01L31/109 ,  H01L31/184 ,  Y02E10/544 ,  Y02P70/521

摘要： An object of the present invention is to provide a group III-V compound semiconductor photo detector comprising an absorption layer having a group III-V compound semiconductor layer containing Sb as a group V constituent element, and an n-type InP window layer, resulting in reduced dark current. The InP layer 23 grown on the absorption layer 23 contains antimony as impurity, due to the memory effect with antimony which is supplied during the growth of a GaAsSb layer of the absorption layer 21. In the group III-V compound semiconductor photo detector 11, the InP layer 23 contains antimony as impurity and is doped with silicon as n-type dopant. Although antimony impurities in the InP layer 23 generate holes, the silicon contained in the InP layer 23 compensates for the generated carriers. As a result, the second portion 23d of the InP layer 23 has sufficient n-type conductivity.

摘要翻译： 本发明的目的是提供一种III-V族化合物半导体光电检测器，其包括具有含有Sb作为V族构成元素的III-V族化合物半导体层和n型InP窗口层的吸收层，得到 在减少的暗电流。 由于在吸收层21的GaAsSb层生长期间提供的锑的记忆效应，在吸收层23上生长的InP层23含有锑作为杂质。在III-V族化合物半导体光电检测器11中， InP层23含有锑作为杂质，并掺杂有硅作为n型掺杂剂。 虽然InP层23中的锑杂质产生空穴，但是包含在InP层23中的硅补偿所生成的载流子。 结果，InP层23的第二部分23d具有足够的n型导电性。

公开(公告)号：US08679543B2

公开(公告)日：2014-03-25

申请号：US13002035

申请日：2009-07-02

申请人： Joseph Bartel ,  Yongfen Chen ,  Eric Tulsky ,  Joseph Treadway

发明人： Joseph Bartel ,  Yongfen Chen ,  Eric Tulsky ,  Joseph Treadway

IPC分类号： A61K9/14

CPC分类号： G01N21/6486 ,  B82Y5/00 ,  B82Y15/00 ,  C01B25/082 ,  C09K11/02 ,  C09K11/565 ,  C09K11/70 ,  C30B7/00 ,  C30B29/40 ,  C30B29/48 ,  C30B29/60 ,  G01N33/588 ,  H01L21/02392 ,  H01L21/02557 ,  H01L21/02601 ,  H01L21/02628 ,  H01L33/06

摘要： Nanocrystals having an indium-based core and methods for making them and using them to construct core-shell nanocrystals are described. These core-shell nanocrystals are highly stable and provide higher quantum yields than known nanocrystals of similar composition, and they provide special advantages for certain applications because of their small size.

摘要翻译： 描述了具有铟基核的纳米晶体及其制备方法和用于构建核壳纳米晶体的方法。 这些核 - 壳纳米晶体是高度稳定的并且提供比已知具有类似组成的纳米晶体更高的量子产率，并且由于它们的小尺寸，它们为某些应用提供了特殊的优点。