Programmable vertical filter for video encoding
    2.
    发明授权
    Programmable vertical filter for video encoding 失效
    用于视频编码的可编程垂直滤波器

    公开(公告)号:US06980598B2

    公开(公告)日:2005-12-27

    申请号:US10081778

    申请日:2002-02-22

    IPC分类号: H04N7/26 H04N7/50 H04N7/12

    摘要: A technique is provided for programmably vertically filtering pixel values of frames of a sequence of video frames. The technique includes separating luminance components and chrominance components of the pixel values within a vertical filter buffer, then vertically filtering luminance components of the pixel values using programmable luminance filter coefficients, and vertically filtering chrominance components of the pixel values using programmable chrominance filter coefficients. The filtered luminance component data and filtered chrominance component data is subsequently merged onto a single luminance/chrominance bus for further filtering and/or encoding. The luminance and chrominance filter coefficients are programmable and may be changed dynamically and repeatedly at picture boundaries. In one embodiment, the programmable vertical filter includes a four tap luminance component filter and a five tap chrominance component filter.

    摘要翻译: 提供了一种用于可编程地垂直滤波视频帧序列的像素值的技术。 该技术包括在垂直滤波器缓冲器内分离像素值的亮度分量和色度分量,然后使用可编程亮度滤波器系数垂直滤波像素值的亮度分量,并使用可编程色度滤波器系数垂直滤波像素值的色度分量。 滤波后的亮度分量数据和经滤波的色度分量数据随后被合并到单个亮度/色度总线上用于进一步的滤波和/或编码。 亮度和色度滤波器系数是可编程的,并且可以在图像边界处动态地和重复地改变。 在一个实施例中,可编程垂直滤波器包括四抽头亮度分量滤波器和五抽头色度分量滤波器。

    Real time clock circuit having an internal clock generator
    3.
    发明授权
    Real time clock circuit having an internal clock generator 失效
    具有内部时钟发生器的实时时钟电路

    公开(公告)号:US07661008B2

    公开(公告)日:2010-02-09

    申请号:US11196111

    申请日:2005-08-03

    IPC分类号: G06F1/00

    CPC分类号: G04G15/006 G04R20/02

    摘要: Under the present invention a real time clock circuit, within a set-top box, is provided with an internal clock generator for generating multiple clock signals. Once generated, a first clock signal is divided into an initial set of values representing time and optionally day/date intervals, and then communicated to a set of clock registers. The initial set of values can then be communicated (directly or via a set of DCR registers) to a display component within the set-top box. Updated clock signals are received by the set of DCR registers from an external source such as a satellite or the like thus making the clock very accurate, and are communicated to the display component. Similar to the initial set of values, the updated set of values could be communicated to the display component directly from the set of DCR registers, or via the set of clock registers.

    摘要翻译: 在本发明中,在机顶盒内的实时时钟电路设置有用于产生多个时钟信号的内部时钟发生器。 一旦生成,第一时钟信号被分成表示时间和可选的日/日间隔的初始值集合,然后传送给一组时钟寄存器。 然后可以将初始值集合(直接或经由一组DCR寄存器)传送到机顶盒内的显示组件。 更新的时钟信号由来自诸如卫星等的外部源的DCR寄存器组接收,从而使时钟非常精确,并被传送到显示组件。 类似于初始值的值,更新的值集合可以直接从DCR寄存器集或通过一组时钟寄存器传送给显示组件。

    Method, system and synchronization circuit for providing hardware component access to a set of data values without restriction
    4.
    发明授权
    Method, system and synchronization circuit for providing hardware component access to a set of data values without restriction 失效
    方法,系统和同步电路,用于不受限制地提供对一组数据值的硬件组件访问

    公开(公告)号:US07017066B2

    公开(公告)日:2006-03-21

    申请号:US10411864

    申请日:2003-04-10

    摘要: The present invention provides hardware-based synchronization within a device such as a set top box so that sets of data values can be communicated between a set of DCR registers operating at a first frequency and a set of clock register operating at a second frequency. Specifically, to communicate an initial set of data values from the set of DCR registers to the set of clock registers, a control signal is stretched and then synchronized with a clock signal having the second frequency. To communicate a current set of data values from the set of clock registers to the set of DCR registers, the control signal is synchronized with a clock signal having the first frequency. By communicating the current set of data values to the first set of registers, a hardware component (e.g., a CPU) can access the current set of data values without restriction.

    摘要翻译: 本发明在诸如机顶盒的设备中提供基于硬件的同步,使得可以在以第一频率工作的一组DCR寄存器和以第二频率操作的一组时钟寄存器之间传送数据值集合。 具体地说,为了将来自DCR寄存器的一组初始的数据值集合传送到时钟寄存器组,控制信号被拉伸,然后与具有第二频率的时钟信号同步。 为了将当前的一组数据值从该组时钟寄存器传送到一组DCR寄存器,控制信号与具有第一频率的时钟信号同步。 通过将当前数据值集合传送到第一组寄存器,硬件组件(例如,CPU)可以无限制地访问当前数据值集合。

    Real time clock circuit having an internal clock generator
    5.
    发明授权
    Real time clock circuit having an internal clock generator 失效
    具有内部时钟发生器的实时时钟电路

    公开(公告)号:US06958953B2

    公开(公告)日:2005-10-25

    申请号:US10437123

    申请日:2003-05-13

    IPC分类号: G04G5/00 G04G15/00 G04C11/02

    CPC分类号: G04G15/006 G04R20/02

    摘要: Under the present invention a real time clock circuit, within a set-top box, is provided with an internal clock generator for generating multiple clock signals. Once generated, a first clock signal is divided into an initial set of values representing time and optionally day/date intervals, and then communicated to a set of clock registers. The initial set of values can then be communicated (directly or via a set of DCR registers) to a display component within the set-top box. Updated clock signals are received by the set of DCR registers from an external source such as a satellite or the like thus making the clock very accurate, and are communicated to the display component. Similar to the initial set of values, the updated set of values could be communicated to the display component directly from the set of DCR registers, or via the set of clock registers.

    摘要翻译: 在本发明中,在机顶盒内的实时时钟电路设置有用于产生多个时钟信号的内部时钟发生器。 一旦生成,第一时钟信号被分成表示时间和可选的日/日间隔的初始值集合,然后传送给一组时钟寄存器。 然后可以将初始值集合(直接或经由一组DCR寄存器)传送到机顶盒内的显示组件。 更新的时钟信号由来自诸如卫星等的外部源的DCR寄存器组接收,从而使时钟非常精确,并被传送到显示组件。 类似于初始值的值,更新的值集合可以直接从DCR寄存器集或通过一组时钟寄存器传送给显示组件。

    Macroblock coding using luminance date in analyzing temporal redundancy of picture, biased by chrominance data
    6.
    发明授权
    Macroblock coding using luminance date in analyzing temporal redundancy of picture, biased by chrominance data 失效
    使用亮度日期分析图像的时间冗余的宏块编码,由色度数据偏置

    公开(公告)号:US06823015B2

    公开(公告)日:2004-11-23

    申请号:US10055395

    申请日:2002-01-23

    IPC分类号: H04B766

    摘要: A technique is provided for encoding macroblocks of a frame of a sequence of video frames initially employing luminance data only to analyze temporal redundancy of the macroblocks within the frame. Upon deciding to code at least one macroblock as a non-intra macroblock, the technique includes considering whether to switch the coding decision for the at least one macroblock from non-intra to intra by evaluating chrominance data of the at least one macroblock. The evaluating of the chrominance data can include determining whether chrominance difference data, obtained by comparing chrominance values of a current macroblock with a reference macroblock, is greater than a user set chrominance difference threshold, and if so then the technique includes switching the macroblock coding decision. As a further qualification, the switching might occur only if the chrominance difference data is also greater than the corresponding luminance difference data.

    摘要翻译: 提供了一种技术,用于对最初采用亮度数据的视频帧序列的帧的宏块进行编码,以分析该帧内的宏块的时间冗余。 在决定将至少一个宏块编码为非帧内宏块时,该技术包括考虑是否通过评估至少一个宏块的色度数据来将非至少一个宏块的编码决定从非帧内切换到帧内。 色度数据的评估可以包括确定通过将当前宏块的色度值与参考宏块进行比较而获得的色差差数据是否大于用户设置的色差差阈值,如果是,则该技术包括切换宏块编码决策 。 作为进一步的鉴定,仅当色差差数据也大于对应的亮度差数据时才可能发生切换。

    Simultaneous vertical spatial filtering and chroma conversion in video images
    8.
    发明授权
    Simultaneous vertical spatial filtering and chroma conversion in video images 有权
    在视频图像中同时进行垂直空间滤波和色度转换

    公开(公告)号:US06941025B2

    公开(公告)日:2005-09-06

    申请号:US09838758

    申请日:2001-04-19

    CPC分类号: H04N9/646

    摘要: Simultaneous vertical spatial filtering and chrominance conversion is achieved with reduced data buffering and simplified filtering circuits by using a single filter stage and hybrid filter coefficients. Data latency is reduced and performance requirements are reduced while avoiding critical signal propagation paths. The filter and buffers are fully compatible with any scan format having consecutively presented lines of image data, including both progressive and interlaced scan formats.

    摘要翻译: 通过使用单个滤波器级和混合滤波器系数,实现减少数据缓冲和简化滤波电路的同时垂直空间滤波和色度转换。 降低数据延迟并降低性能要求,同时避免关键的信号传播路径。 滤波器和缓冲器与具有连续显示的图像数据行的任何扫描格式完全兼容,包括逐行扫描和隔行扫描格式。

    Optimized field-frame prediction error calculation method and apparatus
in a scalable MPEG-2 compliant video encoder
    9.
    发明授权
    Optimized field-frame prediction error calculation method and apparatus in a scalable MPEG-2 compliant video encoder 失效
    可扩展MPEG-2兼容视频编码器中优化的场帧预测误差计算方法和装置

    公开(公告)号:US6081622A

    公开(公告)日:2000-06-27

    申请号:US995350

    申请日:1997-12-22

    摘要: Method and apparatus for encoding digital motion video where a motion vector is formed to describe the translation of a set of picture elements from one picture to another. This is accomplished by calculating a difference or prediction error between a current luminance macroblock and a best match reference luminance macroblock, and between a current chrominance macroblock and a best match reference chrominance macroblock. This is done by selecting a chrominance prediction mode from among a set of chrominance prediction modes. Using the selected chrominance prediction mode, a full or half pel interpolation is calculated and from this a difference or prediction error is calculated between a current chrominance macroblock and a best match reference chrominance macroblock. The required reference chrominance data is fetched, and a chrominance difference or prediction error is calculated. The output is the chrominance difference or prediction error data.

    摘要翻译: 用于编码数字运动视频的方法和装置,其中形成运动矢量以描述一组图像从一幅图像到另一幅图像的平移。 这是通过计算当前亮度宏块和最佳匹配参考亮度宏块之间以及当前色度宏块和最佳匹配参考色度宏块之间的差或预测误差来实现的。 这是通过从一组色度预测模式中选择色度预测模式来完成的。 使用所选择的色度预测模式,计算全或半像素内插,并且由此计算当前色度宏块和最佳匹配参考色度宏块之间的差或预测误差。 获取所需的参考色度数据,并计算色度差或预测误差。 输出是色度差或预测误差数据。