Simultaneous vertical spatial filtering and chroma conversion in video images
    1.
    发明授权
    Simultaneous vertical spatial filtering and chroma conversion in video images 有权
    在视频图像中同时进行垂直空间滤波和色度转换

    公开(公告)号:US06941025B2

    公开(公告)日:2005-09-06

    申请号:US09838758

    申请日:2001-04-19

    CPC分类号: H04N9/646

    摘要: Simultaneous vertical spatial filtering and chrominance conversion is achieved with reduced data buffering and simplified filtering circuits by using a single filter stage and hybrid filter coefficients. Data latency is reduced and performance requirements are reduced while avoiding critical signal propagation paths. The filter and buffers are fully compatible with any scan format having consecutively presented lines of image data, including both progressive and interlaced scan formats.

    摘要翻译: 通过使用单个滤波器级和混合滤波器系数,实现减少数据缓冲和简化滤波电路的同时垂直空间滤波和色度转换。 降低数据延迟并降低性能要求,同时避免关键的信号传播路径。 滤波器和缓冲器与具有连续显示的图像数据行的任何扫描格式完全兼容,包括逐行扫描和隔行扫描格式。

    Cascaded output for an encoder system using multiple encoders
    2.
    发明授权
    Cascaded output for an encoder system using multiple encoders 失效
    使用多个编码器的编码器系统的级联输出

    公开(公告)号:US07936814B2

    公开(公告)日:2011-05-03

    申请号:US10114019

    申请日:2002-03-28

    IPC分类号: H04N7/12

    摘要: Plural encoders operating in parallel to achieve a desired data rate have their respective outputs combined by an autonomously operating arrangement for transfer of data to a direct memory access arrangement from respective encoders in order in response to a signal asserted upon completion of encoding and output of encoded data corresponding to a predetermined portion of input data. Buffering of encoder output can be either internal or external to the encoders. Zero bytes which may be inherently generated at the beginning and end of an encoder output stream may be suppressed to improve encoded signal quality and efficiency.

    摘要翻译: 并行工作以实现所需数据速率的多个编码器具有通过自主操作的结构组合的各自的输出,用于响应于完成编码和输出编码后的信号,从相应的编码器传送数据到直接存储器存取装置 对应于输入数据的预定部分的数据。 编码器输出的缓冲可以是编码器的内部或外部。 可以抑制在编码器输出流的开始和结束处固有地产生的零字节,以改善编码的信号质量和效率。

    Programmable output control of compressed data from encoder
    3.
    发明授权
    Programmable output control of compressed data from encoder 失效
    来自编码器的压缩数据的可编程输出控制

    公开(公告)号:US06720893B2

    公开(公告)日:2004-04-13

    申请号:US10080828

    申请日:2002-02-22

    IPC分类号: H03M700

    CPC分类号: H04N21/23406 H04N21/44004

    摘要: A technique is provided for programmably controlling output of compressed data from, for example, a video encoder. The technique can be implemented within the video encoder and includes buffering the compressed data in a write buffer, followed by transferring the compressed data from the write buffer to a read buffer. At least one programmable output mode is provided for selectively controlling output of the compressed data from the read buffer. When the read buffer is full, the compressed data is stored to the encoder's external memory to await transfer to the read buffer. The at least one programmable mode can include a slave mode, a gated master mode, a multi-cycle speed mode, and a paced master mode, which may be employed individually or in combination. A mechanism for inserting pad bytes of data into the compressed data is also provided.

    摘要翻译: 提供了一种用于可编程地控制来自例如视频编码器的压缩数据的输出的技术。 该技术可以在视频编码器内实现,并且包括将压缩数据缓冲在写缓冲器中,随后将压缩数据从写缓冲器传送到读缓冲器。 提供至少一个可编程输出模式以选择性地控制来自读取缓冲器的压缩数据的输出。 当读取缓冲区已满时,压缩数据将存储到编码器的外部存储器中,以等待传输到读取缓冲区。 至少一个可编程模式可以包括从模式,门控主模式,多循环速度模式和起搏主模式,其可以单独地或组合地使用。 还提供了用于将数据的pad字节插入压缩数据的机制。

    Programmable vertical filter for video encoding
    4.
    发明授权
    Programmable vertical filter for video encoding 失效
    用于视频编码的可编程垂直滤波器

    公开(公告)号:US06980598B2

    公开(公告)日:2005-12-27

    申请号:US10081778

    申请日:2002-02-22

    IPC分类号: H04N7/26 H04N7/50 H04N7/12

    摘要: A technique is provided for programmably vertically filtering pixel values of frames of a sequence of video frames. The technique includes separating luminance components and chrominance components of the pixel values within a vertical filter buffer, then vertically filtering luminance components of the pixel values using programmable luminance filter coefficients, and vertically filtering chrominance components of the pixel values using programmable chrominance filter coefficients. The filtered luminance component data and filtered chrominance component data is subsequently merged onto a single luminance/chrominance bus for further filtering and/or encoding. The luminance and chrominance filter coefficients are programmable and may be changed dynamically and repeatedly at picture boundaries. In one embodiment, the programmable vertical filter includes a four tap luminance component filter and a five tap chrominance component filter.

    摘要翻译: 提供了一种用于可编程地垂直滤波视频帧序列的像素值的技术。 该技术包括在垂直滤波器缓冲器内分离像素值的亮度分量和色度分量,然后使用可编程亮度滤波器系数垂直滤波像素值的亮度分量,并使用可编程色度滤波器系数垂直滤波像素值的色度分量。 滤波后的亮度分量数据和经滤波的色度分量数据随后被合并到单个亮度/色度总线上用于进一步的滤波和/或编码。 亮度和色度滤波器系数是可编程的,并且可以在图像边界处动态地和重复地改变。 在一个实施例中,可编程垂直滤波器包括四抽头亮度分量滤波器和五抽头色度分量滤波器。

    Apparatus for header generation
    5.
    发明授权
    Apparatus for header generation 失效
    用于头部生成的装置

    公开(公告)号:US5526054A

    公开(公告)日:1996-06-11

    申请号:US410951

    申请日:1995-03-27

    IPC分类号: H04N7/26 H04N7/50 H04N7/12

    CPC分类号: H04N19/61 H04N19/00 H04N19/70

    摘要: A method for encoding bitstream headers in a processor where templates for the bitstream header are stored in a processor buffer. The templates are addressable by programmable instructions, and the processor has a status register containing a bit for each header type. The status register is modifiable during the encoding process with a data pattern indicating the headers needed for encoding with the bitstream. In this way when a bit is set to 1 the predefined header type is generated and shipped to the bitstream. The header is generated by processing the header buffer template entries associated with the header type.

    摘要翻译: 一种在处理器中编码比特流报头的方法,其中用于比特流报头的模板被存储在处理器缓冲器中。 模板可通过可编程指令进行寻址,并且处理器具有包含每个标题类型的位的状态寄存器。 状态寄存器在编码处理期间是可修改的,其中具有指示用比特流进行编码所需的头的数据模式。 以这种方式,当一个位设置为1时,生成预定义的标题类型并将其发送到比特流。 通过处理与报头类型相关联的报头缓冲区模板条目来生成报头。

    On-chip dynamic buffer level indicators for digital video encoder
    6.
    发明授权
    On-chip dynamic buffer level indicators for digital video encoder 失效
    用于数字视频编码器的片上动态缓冲器电平指示器

    公开(公告)号:US06961378B1

    公开(公告)日:2005-11-01

    申请号:US09186584

    申请日:1998-11-05

    摘要: Method and encoder for encoding a digital video image stream. The encoding includes spatial compression of still images in the video stream and temporal compression between the still images. The spatial compression is carried out by converting a time domain image of a macroblock to a frequency domain image of the macroblock, taking the discrete cosine transform of the frequency domain image, transforming the discrete cosine transformed macroblock image by a quantization factor, and run length encoding the quantized discrete cosine transformed macroblock image. The temporal compression is carried out by reconstructing the run length encoded, quantized, discrete cosine transformed image of the macroblock, searching for a best match macroblock, and constructing a motion vector between them. This forms a bitstream of run length encoded, quantized, discrete cosine transform macroblocks and of motion vectors. This bitstream is passed to and through an external buffer to a transmission medium. The number encoded bits read by a host from the external buffer is fed back to the encoder for calculation in real time of a dynamic buffer level indicator indicative of the fullness of the external buffer. The encoder may generate a BUFFER—EMPTY flag, BUFFER—ALMOST—FULL flag and/or BUFFER—FULL flag for the host.

    摘要翻译: 用于对数字视频图像流进行编码的方法和编码器。 编码包括视频流中的静止图像的空间压缩和静止图像之间的时间压缩。 空间压缩通过将宏块的时域图像转换为宏块的频域图像,以频域图像的离散余弦变换为单位,将离散余弦变换的宏块图像变换为量化因子,运行长度 对量化的离散余弦变换宏块图像进行编码。 通过重建宏块的游程长度编码,量化,离散余弦变换图像,搜索最佳匹配宏块,并在它们之间构建运动矢量来执行时间压缩。 这形成游程长度编码,量化,离散余弦变换宏块和运动矢量的比特流。 该比特流被传递到外部缓冲器并传送到传输介质。 主机从外部缓冲器读取的编码比特数被反馈给编码器,用于实时地计算表示外部缓冲器的饱和度的动态缓冲器级别指示符。 编码器可以生成BUFFER EMPTY标志,BUFFER - ALMOST - FULL标志和/或BUFFER - FULL 标志为主机。

    Motion estimation architecture for area and power reduction
    7.
    发明授权
    Motion estimation architecture for area and power reduction 失效
    用于区域和功率降低的运动估计架构

    公开(公告)号:US6020934A

    公开(公告)日:2000-02-01

    申请号:US46291

    申请日:1998-03-23

    摘要: A method for compensating for reduced picture quality when combining a multi-chip encoding chipset into a single integrated semiconductor IC. The method includes additional functions provided on the single IC to compensate for the negative effects on picture quality produced as a result of rounding 8 bit luminance pixel data to 5 bits, where the luminance data values are supplied as input to the search function. The additional functions are collectively referred to as motion biasing and are applied to influence the choice of a "best match" motion type, which is well known in the art. The biasing is performed by the addition of a weight factor to a total difference result that is calculated by the search function. The biasing is applied only for the purpose of influencing the choice of a reference frame that is not necessarily the frame which produces an optimal motion vector, but rather will result in using fewer bits to encode macroblocks.

    摘要翻译: 一种用于在将多芯片编码芯片组合成单个集成半导体IC时补偿降低的图像质量的方法。 该方法包括在单个IC上提供的附加功能,以补偿由于将8位亮度像素数据舍入到5位而产生的图像质量的负面影响,其中将亮度数据值作为输入提供给搜索功能。 附加功能统称为运动偏移,并且被应用以影响本领域中公知的“最佳匹配”运动类型的选择。 通过将加权因子加到通过搜索函数计算的总差值结果来执行偏置。 偏置仅用于影响参考帧的选择,该参考帧不一定是产生最佳运动矢量的帧,而是将导致使用较少位来编码宏块。

    Character scrolling method and apparatus
    8.
    发明授权
    Character scrolling method and apparatus 失效
    字符滚动方法和装置

    公开(公告)号:US5477240A

    公开(公告)日:1995-12-19

    申请号:US864386

    申请日:1992-04-07

    CPC分类号: G09B5/065 G09G5/06 G09G5/346

    摘要: A method for scrolling, at a desired rate and in a given direction, a graphic character on a display having a predetermined number of actual scan lines and a vertical blanking interval occurring between successive display of all the actual horizontal scan lines of the display, involves the creation of fractional scan lines between successive vertical blanking intervals, the identification of leading and trailing edges of the character and the selective changing of the color or shading of pixels of the leading and trailing edges to effect scolling of the character.

    摘要翻译: 一种用于以期望的速率和给定的方向滚动显示器上的图形字符的方法,该显示器具有预定数量的实际扫描线和在显示器的所有实际水平扫描线的连续显示之间出现的垂直消隐间隔,涉及 在连续的垂直消隐间隔之间创建分数扫描线,识别字符的前沿和后沿以及前后边缘的像素的颜色或阴影的选择性变化,以实现字符的切割。

    Intersystem channel paging system having a circuit for executing
synchronous or asynchronous instructions for transferring messages
between devices and a shared storage
    9.
    发明授权
    Intersystem channel paging system having a circuit for executing synchronous or asynchronous instructions for transferring messages between devices and a shared storage 失效
    具有用于执行用于在设备和共享存储器之间传送消息的同步或异步指令的电路的系统间通道寻呼系统

    公开(公告)号:US5410655A

    公开(公告)日:1995-04-25

    申请号:US305502

    申请日:1994-09-13

    CPC分类号: G06F13/126

    摘要: An apparatus for intersystem I/O channel paging. The I/O channel through an I/O channel adapter provides communication between a central processor, an I/O processor, and a shared electronic storage device. The central processor and I/O processor are each enabled for recognizing specific instructions. The intersystem channel may be implemented in the form of a page chain table. Either process is capable of constructing a page chain table in the shared electronic storage device, upon receipt of appropriate instructions. The central processor or I/O processor signals the I/O channel adapter with identification of a page chain table to select. The I/O channel adapter fetches table entries and executes the table. The I/O channel adapter initiates I/O activity upon execution of the table. The I/O channel is not dependent upon the central processor or I/O processor for fetching or executing instructions, rather it acts independent of the processors once the page chain table is created. Flags set in the table serve as a disconnection mechanism for the I/O channel paging system. The I/O channel paging mechanism may operate synchronously or asynchronously.

    摘要翻译: 用于系统间I / O通道寻呼的装置。 通过I / O通道适配器的I / O通道提供中央处理器,I / O处理器和共享电子存储设备之间的通信。 每个中央处理器和I / O处理器均可用于识别特定的指令。 系统间通道可以以页链表的形式来实现。 任何一个进程都能够在收到适当的指令后在共享电子存储设备中构建页链表。 中央处理器或I / O处理器向I / O通道适配器发送信号以识别页链表进行选择。 I / O通道适配器提取表条目并执行表。 I / O通道适配器在执行表时启动I / O活动。 I / O通道不依赖于用于获取或执行指令的中央处理器或I / O处理器,而是在创建页链表之后独立于处理器。 表中设置的标志用作I / O通道寻呼系统的断开机制。 I / O通道寻呼机制可以同步或异步地进行。