Flow control timeout mechanism to detect PCI-express forward progress blockage
    1.
    发明授权
    Flow control timeout mechanism to detect PCI-express forward progress blockage 有权
    流量控制超时机制,用于检测PCI-Express前进进程阻塞

    公开(公告)号:US08151145B2

    公开(公告)日:2012-04-03

    申请号:US12061667

    申请日:2008-04-03

    申请人: John R. Feehrer

    发明人: John R. Feehrer

    IPC分类号: G06F11/00

    摘要: A method for detecting lack of forward progress in a PCI Express includes a step in which a data flow measurement is received or performed. This data flow measurement provides the capacity of the connected Switch or Endpoint device to receive data packets from a Root Complex transmit channel. An error is logged when the data flow measurement does not substantially change in a predetermined period of time. A recovery protocol is executed after logging of the error. A system implementing the method of the invention is also provided.

    摘要翻译: 用于检测PCI Express中的前进进程缺乏的方法包括接收或执行数据流测量的步骤。 该数据流测量提供连接的交换机或端点设备从根复合发送信道接收数据分组的容量。 当数据流测量在预定时间段内基本上不会改变时,会记录错误。 在记录错误后执行恢复协议。 还提供了实现本发明的方法的系统。

    Methods and apparatus for performing remote access commands between nodes
    2.
    发明授权
    Methods and apparatus for performing remote access commands between nodes 有权
    在节点之间执行远程访问命令的方法和装置

    公开(公告)号:US08090801B1

    公开(公告)日:2012-01-03

    申请号:US10767182

    申请日:2004-01-29

    IPC分类号: G06F15/16 G06F15/173 G06F9/46

    CPC分类号: G06F9/544

    摘要: A system, methods and apparatus perform remote access commands between nodes and allow preemption of context resources in an architecture such as Infiniband. The system detects an original request in a request queue for a data access task to access data from a first node to a second node and issues a first request from a first node to a second node. The first request requests the data access task be performed between the first node and the second node. The system receives, at the first node, a first response from the second node that partially completes the data access task. The system issues at least one subsidiary request from the first node to the second node to further complete the data access task between the first node and the second node. The subsidiary request(s) are based on an amount of partial completion of the data access task between the first node and the second node. The system receives, from the second node in response to the subsidiary request, at least one corresponding subsidiary response that further completes the data access task between the first node and the second node. Reponses are limited in size to a data allotment, such that a large data access request may be broken into several smaller subsidiary data access request response sequences, thus allowing preemption of context resources in between processing of request response pairs.

    摘要翻译: 系统,方法和装置在节点之间执行远程访问命令,并允许在诸如Infiniband的架构中抢占上下文资源。 系统检测用于数据访问任务的请求队列中的原始请求,以访问从第一节点到第二节点的数据,并从第一节点向第二节点发出第一请求。 第一请求请求在第一节点和第二节点之间执行数据访问任务。 系统在第一节点处接收来自第二节点的部分完成数据访问任务的第一响应。 系统发出从第一节点到第二节点的至少一个辅助请求,以进一步完成第一节点和第二节点之间的数据访问任务。 辅助请求基于第一节点和第二节点之间的数据访问任务的部分完成量。 所述系统响应于所述辅助请求从所述第二节点接收至少一个对应的辅助响应,所述至少一个对应的辅助响应进一步完成所述第一节点和所述第二节点之间的数据访问任务。 报文的大小受到数据分配的限制,使得大的数据访问请求可能被分解成若干较小的辅助数据访问请求响应序列,从而允许在请求响应对的处理之间抢占上下文资源。

    Method and system of preventing silent data corruption
    3.
    发明授权
    Method and system of preventing silent data corruption 有权
    防止静默数据损坏的方法和系统

    公开(公告)号:US08839268B2

    公开(公告)日:2014-09-16

    申请号:US12027549

    申请日:2008-02-07

    申请人: John R. Feehrer

    发明人: John R. Feehrer

    CPC分类号: G06K7/0008 G06K7/10039

    摘要: A method and system of avoiding silent data corruption in a request-response messaging system where a requester relies on tags to match request messages with response messages. The silent data corruption occurring if the requester process a response message after a tag used with the response message was reused with another request message.

    摘要翻译: 一种在请求 - 响应消息系统中避免静默数据损坏的方法和系统,其中请求者依赖标签将请求消息与响应消息相匹配。 如果在与响应消息一起使用的标签之后,请求者处理响应消息,则会发生无声数据损坏,并重新使用另一个请求消息。

    PCI-express system
    4.
    发明授权
    PCI-express system 有权
    PCI-express系统

    公开(公告)号:US07689751B2

    公开(公告)日:2010-03-30

    申请号:US12031913

    申请日:2008-02-15

    申请人: John R. Feehrer

    发明人: John R. Feehrer

    IPC分类号: G06F3/00 G06F13/00

    CPC分类号: G06F13/24

    摘要: A method and system to facilitate Peripheral Component Interconnect Express (PCIe). The PCIe may be facilitated in such as way as to limit pins consumed by a Root Complex, switch, or other chipset included on the same die a central processing unit (CPU). A slot interface card (SIC) or other devices having less expensive pins may be used to connect to and communicate with the slot.

    摘要翻译: 一种促进外围组件互连Express(PCIe)的方法和系统。 可以以这样的方式促进PCIe,以便限制由根复合体,交换机或包括在同一裸片上的其他芯片组消耗的引脚的中央处理器(CPU)。 可以使用具有较便宜引脚的插槽接口卡(SIC)或其他设备来连接并与插槽通信。

    Interrupt processing unit for preventing interrupt loss
    5.
    发明授权
    Interrupt processing unit for preventing interrupt loss 有权
    用于防止中断丢失的中断处理单元

    公开(公告)号:US09026705B2

    公开(公告)日:2015-05-05

    申请号:US13571051

    申请日:2012-08-09

    IPC分类号: G06F13/24 G06F9/48

    摘要: Techniques are disclosed relating to systems that allow sending and receiving of interrupts between processing elements. In various embodiments, a system includes an interrupt processing unit that in turn includes various indicators corresponding to processing elements. In some embodiments, the interrupt processing unit may be configured to receive an interrupt and determine whether a first processing element associated with the interrupt is available to receive interrupts. The system may initiate a corrective action if the first processing element is not available to receive interrupts. In some embodiments, the corrective action may include redirecting the interrupt to a second processing element. In some embodiments, the interrupt processing unit may include a dropped interrupt management register to store information corresponding to the second processing element. In some embodiments, the corrective action may include altering the power state of the first processing element such that it becomes available to receive interrupts.

    摘要翻译: 公开了涉及允许发送和接收处理元件之间的中断的系统的技术。 在各种实施例中,系统包括中断处理单元,该中断处理单元又包括对应于处理元件的各种指示符。 在一些实施例中,中断处理单元可以被配置为接收中断并且确定与该中断相关联的第一处理单元是否可用于接收中断。 如果第一处理元件不可用于接收中断,则系统可以发起校正动作。 在一些实施例中,校正动作可以包括将中断重定向到第二处理元件。 在一些实施例中,中断处理单元可以包括丢弃的中断管理寄存器来存储对应于第二处理单元的信息。 在一些实施例中,校正动作可以包括改变第一处理元件的功率状态,使得其可用于接收中断。

    System and method for recovery from address errors
    7.
    发明授权
    System and method for recovery from address errors 失效
    从地址错误中恢复的系统和方法

    公开(公告)号:US06405322B1

    公开(公告)日:2002-06-11

    申请号:US09290942

    申请日:1999-04-13

    IPC分类号: G06F1216

    摘要: A device and method for recovery from address errors is described. When an address error is detected on a local channel, such as a local bus, the coherency states of one or more lines of cache memory associated with the local channel are read, and actions are taken in response. Reading of coherency states ranges from a complete and active interrogation of all cache lines, to a selective and passive interrogation, such as in responding to snoop requests. If the data state consistency is unknown, such as when the MESI state is Modified (M) or Exclusive (E), then the corresponding data in main memory is poisoned. Poisoning may be accomplished by writing a detectable but unrecoverable error pattern in the main memory. Alternatively, the same effect may be accomplished by signaling a hard error on the system bus. If the data state consistency of an interrogated cache line is Shared (S) or Invalid (I), the line may be ignored or the line marked invalid. If the state of the cached line is valid and consistent, such as the “Modified uncached” (Mu) state in a MuMESI protocol, then the line may be written to main memory or provided to a snoop requester.

    摘要翻译: 描述用于从地址错误中恢复的设备和方法。 当在本地信道(例如本地总线)上检测到地址错误时,读取与本地信道相关联的一行或多行高速缓冲存储器的一致性状态,并作出响应。 相关性状态的读取范围从所有高速缓存行的完整和主动询问,到选择性和被动询问,例如响应窥探请求。 如果数据状态一致性未知,例如当MESI状态为M(M)或Exclusive(E)时,则主存储器中的相应数据中毒。 中毒可以通过在主存储器中写入可检测但不可恢复的错误模式来实现。 或者,通过在系统总线上发出硬错误来实现相同的效果。 如果询问的高速缓存行的数据状态一致性为Shared(S)或Invalid(I),则该行可能会被忽略或标记为无效的行。 如果缓存行的状态是有效且一致的,例如MuMESI协议中的“Modified uncached”(Mu)状态,则该行可以写入主存储器或提供给窥探请求者。

    VALIDATING MESSAGE-SIGNALED INTERRUPTS
    9.
    发明申请
    VALIDATING MESSAGE-SIGNALED INTERRUPTS 有权
    验证信息信号中断

    公开(公告)号:US20130080673A1

    公开(公告)日:2013-03-28

    申请号:US13245541

    申请日:2011-09-26

    IPC分类号: G06F13/24

    CPC分类号: G06F13/24 G06F21/53

    摘要: The disclosed embodiments provide a system that validates message-signaled interrupts. During operation, the system receives a message-signaled interrupt from a requesting device. This message-signaled interrupt includes an interrupt vector that identifies an interrupt, and is accompanied by an identification tag that identifies the source of the interrupt. The system uses the interrupt vector to access a stored tag from a tracking mechanism that associates source devices with their assigned interrupt vector(s). The system then compares the identification tag and the stored tag to validate the message-signaled interrupt.

    摘要翻译: 所公开的实施例提供了一种验证消息信号中断的系统。 在操作期间,系统从请求设备接收消息信号中断。 该消息信号中断包括一个识别中断的中断向量,并伴随着识别中断源的识别标签。 系统使用中断向量从跟踪机制访问存储的标签,该机制将源设备与其分配的中断向量相关联。 然后,系统比较识别标签和存储的标签,以验证消息信号中断。

    FLOW CONTROL TIMEOUT MECHANISM TO DETECT PCI-EXPRESS FORWARD PROGRESS BLOCKAGE
    10.
    发明申请
    FLOW CONTROL TIMEOUT MECHANISM TO DETECT PCI-EXPRESS FORWARD PROGRESS BLOCKAGE 有权
    流量控制超时机制,用于检测PCI-EXPRESS前进进程阻塞

    公开(公告)号:US20090254692A1

    公开(公告)日:2009-10-08

    申请号:US12061667

    申请日:2008-04-03

    申请人: John R. Feehrer

    发明人: John R. Feehrer

    IPC分类号: G06F13/36

    摘要: A method for detecting lack of forward progress in a PCI Express includes a step in which a data flow measurement is received or performed. This data flow measurement provides the capacity of the connected Switch or Endpoint device to receive data packets from a Root Complex transmit channel. An error is logged when the data flow measurement does not substantially change in a predetermined period of time. A recovery protocol is executed after logging of the error. A system implementing the method of the invention is also provided.

    摘要翻译: 用于检测PCI Express中的前进进程缺乏的方法包括接收或执行数据流测量的步骤。 该数据流测量提供连接的交换机或端点设备从根复合发送信道接收数据分组的容量。 当数据流测量在预定时间段内基本上不会改变时,会记录错误。 在记录错误后执行恢复协议。 还提供了实现本发明的方法的系统。