公开(公告)号：US08775906B2

公开(公告)日：2014-07-08

申请号：US13611909

申请日：2012-09-12

申请人： John S. Dodson ,  Benjiman L. Goodman ,  Steven J. Hnatko ,  Kenneth L. Wright

发明人： John S. Dodson ,  Benjiman L. Goodman ,  Steven J. Hnatko ,  Kenneth L. Wright

IPC分类号： G11C29/42 ,  G06F11/10 ,  G11C29/54 ,  G11C29/04

CPC分类号： G06F11/1076 ,  G06F11/1064 ,  G06F12/0815 ,  G06F12/0895 ,  G11C2029/0411

摘要： Mechanisms are provided for efficient storage of meta-bits within a system memory. The mechanisms combine an L/G bit and an SUE bit to form meta-bits. The mechanisms then determine the local/global state of a cache line on the first cycle of data. The mechanisms forward the data to the requesting cache, and the requesting cache may reissue the request globally based on the local/global state of the cache line. The mechanisms then determine the special uncorrectable error state of the cache line on the second or subsequent cycle of data. The mechanisms perform error processing regardless of whether the request was reissued globally.

公开(公告)号：US20130212330A1

公开(公告)日：2013-08-15

申请号：US13371906

申请日：2012-02-13

申请人： Mark A. Brittain ,  John S. Dodson ,  Stephen J. Powell ,  Eric E. Retter ,  Jeffrey A. Stuecheli

发明人： Mark A. Brittain ,  John S. Dodson ,  Stephen J. Powell ,  Eric E. Retter ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/00

CPC分类号： G11C11/40607 ,  G06F13/1626 ,  G06F13/1689

摘要： A memory system and data processing system for controlling memory refresh operations in dynamic random access memories. The memory controller comprises logic that: tracks a time remaining before a scheduled time for performing a high priority, high latency operation a first memory rank of the memory system; responsive to the time remaining reaching a pre-established early notification time before the schedule time for performing the high priority, high latency operation, biases the re-order queue containing memory access operations targeting the plurality of ranks to prioritize scheduling of any first memory access operations that target the first memory rank. The logic further: schedules the first memory access operations to the first memory rank for early completion relative to other memory access operations in the re-order queue that target other memory ranks; and performs the high priority, high latency operation at the first memory rank at the scheduled time.

摘要翻译： 一种用于控制动态随机存取存储器中的存储器刷新操作的存储器系统和数据处理系统。 存储器控制器包括以下逻辑：跟踪在用于执行高优先级高等待时间操作的预定时间之前的剩余时间存储器系统的第一存储器等级; 响应于在执行高优先级高等待时间操作的调度时间之前达到预先建立的早期通知时间的时间，偏置包含针对多个等级的存储器访问操作的重新排序队列，以优先排序任何第一存储器访问 针对第一个内存排名的操作。 该逻辑进一步：将第一存储器访问操作调度到第一存储器等级以便相对于针对其他存储器排序的重新排序队列中的其他存储器访问操作来提前完成; 并且在预定时间在第一存储器等级执行高优先级，高延迟操作。

公开(公告)号：US08489807B2

公开(公告)日：2013-07-16

申请号：US12959637

申请日：2010-12-03

申请人： John S. Dodson ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  Stephen Powell ,  Jeffrey A. Stuecheli

发明人： John S. Dodson ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  Stephen Powell ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/00

CPC分类号： G11C11/40603

摘要： Techniques for performing refresh operations is disclosed. In response to a completion of a memory operation, a determination is made whether or not a refresh backlog count is greater than a first predetermined value. In a determination that the refresh backlog count is greater than the first predetermined value, a refresh operation is performed as soon as possible. In a determination that the refresh backlog count is not greater than the first predetermined value, a refresh operation is performed after a delay of an idle count value.

摘要翻译： 公开了用于执行刷新操作的技术。 响应于存储器操作的完成，确定刷新积压计数是否大于第一预定值。 在确定刷新积压计数大于第一预定值的情况下，尽可能快地执行刷新操作。 在确定刷新积压计数不大于第一预定值的情况下，在空闲计数值的延迟之后执行刷新操作。

公开(公告)号：US20130151929A1

公开(公告)日：2013-06-13

申请号：US13313364

申请日：2011-12-07

申请人： John S. Dodson ,  Benjiman L. Goodman ,  Steven J. Hnatko ,  Kenneth L. Wright

发明人： John S. Dodson ,  Benjiman L. Goodman ,  Steven J. Hnatko ,  Kenneth L. Wright

IPC分类号： G06F11/16 ,  G06F12/08

CPC分类号： G06F11/1076 ,  G06F11/1064 ,  G06F12/0815 ,  G06F12/0895 ,  G11C2029/0411

摘要： Mechanisms are provided for efficient storage of meta-bits within a system memory. The mechanisms combine an L/G bit and an SUE bit to form meta-bits. The mechanisms then determine the local/global state of a cache line on the first cycle of data. The mechanisms forward the data to the requesting cache, and the requesting cache may reissue the request globally based on the local/global state of the cache line. The mechanisms then determine the special uncorrectable error state of the cache line on the second or subsequent cycle of data. The mechanisms perform error processing regardless of whether the request was reissued globally.

摘要翻译： 提供了用于在系统存储器内有效存储元位的机制。 这些机制将L / G位和SUE位组合以形成元位。 机制然后在第一个数据周期上确定高速缓存行的本地/全局状态。 这些机制将数据转发到请求的高速缓存，并且请求高速缓存可以基于高速缓存行的本地/全局状态全局重新发出请求。 这些机制然后在数据的第二个或随后的周期中确定高速缓存行的特殊的不可校正错误状态。 机制执行错误处理，而不管请求是否在全球重新发布。

公开(公告)号：US20130111103A1

公开(公告)日：2013-05-02

申请号：US13283956

申请日：2011-10-28

申请人： John S. Dodson ,  Randal C. Swanberg

发明人： John S. Dodson ,  Randal C. Swanberg

IPC分类号： G06F12/02 ,  G06F12/16 ,  G06F12/06

CPC分类号： G06F12/0246 ,  G06F2212/7202

摘要： A memory configured to provide a write requestor with a direct write programming interface to a disk device. A first persistent memory is configured for designating at least a portion its memory locations as central processing unit (CPU) load storable memory. The first persistent memory is also configured for receiving write data from the write requestor, for storing the write data in the CPU load storable memory, and for returning a write completion message to the write requestor in response to the storing completing. The memory also includes a second persistent memory that includes the disk device, and a controller in communication with the first and second persistent memories. The controller is configured for detecting the storing of the write data to the CPU load storable memory and for copying the write data to the second persistent memory in response to detecting the storing of the write data.

摘要翻译： 配置用于向写请求者提供与盘设备的直接写入编程接口的存储器。 第一持久存储器被配置为将其存储器位置的至少一部分指定为中央处理单元（CPU）加载可存储存储器。 第一持久存储器还被配置为从写入请求器接收写入数据，用于将写入数据存储在CPU可加载存储器中，并且响应于存储完成而将写入完成消息返回到写入请求者。 存储器还包括包括磁盘设备的第二持久存储器以及与第一和第二持久存储器通信的控制器。 控制器被配置为响应于检测到写入数据的存储而检测写入数据到CPU负载可存储存储器的存储器并将写入数据复制到第二持久存储器。

公开(公告)号：US20120144105A1

公开(公告)日：2012-06-07

申请号：US12959637

申请日：2010-12-03

申请人： John S. Dodson ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  Stephen Powell ,  Jeffrey A. Stuecheli

发明人： John S. Dodson ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  Stephen Powell ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/00

CPC分类号： G11C11/40603

摘要： A method for performing refresh operations is disclosed. In response to a completion of a memory operation, a determination is made whether or not a refresh backlog count is greater than a first predetermined value. In a determination that the refresh backlog count is greater than the first predetermined value, a refresh operation is performed as soon as possible. In a determination that the refresh backlog count is not greater than the first predetermined value, a refresh operation is performed after a delay of an idle count value.

摘要翻译： 公开了一种执行刷新操作的方法。 响应于存储器操作的完成，确定刷新积压计数是否大于第一预定值。 在确定刷新积压计数大于第一预定值的情况下，尽可能快地执行刷新操作。 在确定刷新积压计数不大于第一预定值的情况下，在空闲计数值的延迟之后执行刷新操作。

公开(公告)号：US5623694A

公开(公告)日：1997-04-22

申请号：US316978

申请日：1994-10-03

申请人： Ravi K. Arimilli ,  John S. Dodson ,  Jerry D. Lewis

发明人： Ravi K. Arimilli ,  John S. Dodson ,  Jerry D. Lewis

IPC分类号： G06F13/00 ,  G06F11/14 ,  G06F13/40

CPC分类号： G06F13/4054 ,  G06F11/1407

摘要： A data processing system includes one or more processing units, a memory subsystem, and one or more input/output channel controllers, wherein each of the input/output channel controllers include the capability of speculative input/output execution. The speculative I/O execution technique according to the present invention may include several options. The speculative execution in the IOCC begins after receiving a raw address even though the operation can still be remotely retried. The programmed I/O latency time is reduced significantly due to the early speculative commencement of the IOCC operation. The IOCC may have to abort the speculative operation if a remote flow control retry is received. If, however, no retry is received then significant time is saved because the speculative operation proceeds.

摘要翻译： 数据处理系统包括一个或多个处理单元，存储器子系统和一个或多个输入/输出通道控制器，其中每个输入/输出通道控制器包括投机输入/输出执行的能力。 根据本发明的推测性I / O执行技术可以包括若干选项。 即使该操作仍可远程重试，IOCC的投机执行在收到原始地址后开始。 由于IOCC运营的早期投机开始，编程的I / O延迟时间显着降低。 如果接收到远程流量控制重试，IOCC可能必须中止推测操作。 然而，如果没有收到重试，那么由于投机操作进行而节省了大量时间。

公开(公告)号：US20130151867A1

公开(公告)日：2013-06-13

申请号：US13314379

申请日：2011-12-08

申请人： John S. Dodson ,  Karthick Rajamani ,  Eric E. Retter ,  Kenneth L. Wright

发明人： John S. Dodson ,  Karthick Rajamani ,  Eric E. Retter ,  Kenneth L. Wright

IPC分类号： G06F1/26 ,  G06F12/00

CPC分类号： G06F3/0644 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/3275 ,  G06F13/16 ,  G11C5/147 ,  G11C11/4074 ,  Y02D10/14

摘要： A technique for memory command throttling in a partitioned memory subsystem includes accepting, by a master memory controller included in multiple memory controllers, a synchronization command. The synchronization command includes command data that includes an associated synchronization indication (e.g., a synchronization bit or bits) for each of the multiple memory controllers and each of the multiple memory controllers controls a respective partition of the partitioned memory subsystem. In response to receiving the synchronization command, the master memory controller forwards the synchronization command to the multiple memory controllers. In response to receiving the forwarded synchronization command each of the multiple memory controllers de-asserts an associated status bit. In response to receiving the forwarded synchronization command, each of the multiple memory controllers determines whether the associated synchronization indication is asserted. Each of the multiple memory controllers with the asserted associated synchronization indication then transmits the forwarded synchronization command to associated power control logic.

摘要翻译： 在分区存储器子系统中用于存储器命令调节的技术包括由包含在多个存储器控制器中的主存储器控制器接受同步命令。 同步命令包括命令数据，其包括用于多个存储器控制器中的每一个的相关联的同步指示（例如，同步位或位），并且多个存储器控制器中的每一个控制分区存储器子系统的相应分区。 响应于接收到同步命令，主存储器控制器将同步命令转发到多个存储器控制器。 响应于接收到转发的同步命令，多个存储器控制器中的每个存储器控制器断言相关联的状态位。 响应于接收到转发的同步命令，多个存储器控制器中的每一个确定相关联的同步指示是否被断言。 具有断言的相关同步指示的多个存储器控制器中的每一个然后将转发的同步命令发送到相关联的功率控制逻辑。

公开(公告)号：US08909874B2

公开(公告)日：2014-12-09

申请号：US13371906

申请日：2012-02-13

申请人： Mark A. Brittain ,  John S. Dodson ,  Stephen J. Powell ,  Eric E. Retter ,  Jeffrey A. Stuecheli

发明人： Mark A. Brittain ,  John S. Dodson ,  Stephen J. Powell ,  Eric E. Retter ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G11C11/40607 ,  G06F13/1626 ,  G06F13/1689

摘要： A memory system and data processing system for controlling memory refresh operations in dynamic random access memories. The memory controller comprises logic that: tracks a time remaining before a scheduled time for performing a high priority, high latency operation a first memory rank of the memory system; responsive to the time remaining reaching a pre-established early notification time before the schedule time for performing the high priority, high latency operation, biases the re-order queue containing memory access operations targeting the plurality of ranks to prioritize scheduling of any first memory access operations that target the first memory rank. The logic further: schedules the first memory access operations to the first memory rank for early completion relative to other memory access operations in the re-order queue that target other memory ranks; and performs the high priority, high latency operation at the first memory rank at the scheduled time.

摘要翻译： 一种用于控制动态随机存取存储器中的存储器刷新操作的存储器系统和数据处理系统。 存储器控制器包括以下逻辑：跟踪在用于执行高优先级高等待时间操作的预定时间之前的剩余时间存储器系统的第一存储器等级; 响应于在执行高优先级高等待时间操作的调度时间之前达到预先建立的早期通知时间的时间，偏置包含针对多个等级的存储器访问操作的重新排序队列，以优先排序任何第一存储器访问 针对第一个内存排名的操作。 该逻辑进一步：将第一存储器访问操作调度到第一存储器等级以便相对于针对其他存储器排序的重新排序队列中的其他存储器访问操作来提前完成; 并且在预定时间在第一存储器等级执行高优先级，高延迟操作。

公开(公告)号：US08775904B2

公开(公告)日：2014-07-08

申请号：US13313364

申请日：2011-12-07

申请人： John S. Dodson ,  Benjiman L. Goodman ,  Steven J. Hnatko ,  Kenneth L. Wright

发明人： John S. Dodson ,  Benjiman L. Goodman ,  Steven J. Hnatko ,  Kenneth L. Wright

IPC分类号： G11C29/42 ,  G06F11/10 ,  G11C29/54 ,  G11C29/04

CPC分类号： G06F11/1076 ,  G06F11/1064 ,  G06F12/0815 ,  G06F12/0895 ,  G11C2029/0411

摘要： Mechanisms are provided for efficient storage of meta-bits within a system memory. The mechanisms combine an L/G bit and an SUE bit to form meta-bits. The mechanisms then determine the local/global state of a cache line on the first cycle of data. The mechanisms forward the data to the requesting cache, and the requesting cache may reissue the request globally based on the local/global state of the cache line. The mechanisms then determine the special uncorrectable error state of the cache line on the second or subsequent cycle of data. The mechanisms perform error processing regardless of whether the request was reissued globally.

摘要翻译： 提供了用于在系统存储器内有效存储元位的机制。 这些机制将L / G位和SUE位组合以形成元位。 机制然后在第一个数据周期上确定高速缓存行的本地/全局状态。 这些机制将数据转发到请求的高速缓存，并且请求高速缓存可以基于高速缓存行的本地/全局状态全局重新发出请求。 这些机制然后在数据的第二个或随后的周期中确定高速缓存行的特殊的不可校正错误状态。 机制执行错误处理，而不管请求是否在全球重新发布。