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1.发明授权Processing columns in a database accelerator while preserving row-based architecture 有权在数据库加速器中处理列，同时保留基于行的体系结构公开(公告)号：US09087095B2
公开(公告)日：2015-07-21
申请号：US13529367
申请日：2012-06-21
CPC分类号： G06F17/30315 , G06F17/30312 , G06F17/30318 , G06F17/30424
摘要： Database processing using columns to present to a processing unit decompressed column data without changing the underlying row-based database architecture. For some embodiments, a database accelerator is used to efficiently process the columns of a database and output tuples to a processing unit's memory, such that the columns can be quickly processed (with the advantages of a column-based architecture) to create tuples of requested data, but without having to depart from a row-based architecture at the processing unit level or having decompressed data scattered throughout the processing unit's memory.
摘要翻译： 数据库处理使用列向处理单元提供解压缩列数据，而无需更改底层的行数据库体系结构。 对于一些实施例，使用数据库加速器来有效地处理数据库的列并将元组输出到处理单元的存储器，使得可以快速处理列（具有基于列的体系结构的优点）来创建所请求的元组 数据，但不必在处理单元级别离开基于行的架构，或者具有分散在处理单元的存储器中的解压缩数据。
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2.发明授权Apparatus for executing programs for a first computer architechture on a computer of a second architechture 有权用于在第二建筑物的计算机上执行用于第一计算机建筑物的程序的装置公开(公告)号：US08127121B2
公开(公告)日：2012-02-28
申请号：US11904007
申请日：2007-09-25
申请人： John S. Yates, Jr. , Matthew F. Storch , Sandeep Nijhawan , Dale R. Jurich , Korbin S. Van Dyke
发明人： John S. Yates, Jr. , Matthew F. Storch , Sandeep Nijhawan , Dale R. Jurich , Korbin S. Van Dyke
CPC分类号： G06F9/45554 , G06F9/30174 , G06F9/30189 , G06F9/3861
摘要： Executing programs coded in an instruction set of a first computer on a computer of a second, different architecture. An operating system maintains an association between each one of a set of concurrent threads and a set of computer resources of the thread's context. Without modifying a pre-existing operating system of the computer, an entry exception is establishing to be raised on each entry to the operating system at a specified entry point or on a specified condition. The entry exception has an associated entry handler programmed to save a context of an interrupted thread and modify the thread context before delivering the modified context to the operating system. A resumption exception is established to be raised on each resumption from the operating system complementary to one of the specified entries. The resumption exception has an associated exit handler programmed to restore the context saved by a corresponding execution of the entry handler. The entry exception, exit exception, entry handler, and exit handler are cooperatively designed to maintain an association between a one of the threads and an extended context of the thread through a context change induced by the operating system, the extended context including resources of the computer associated with the thread beyond those resources whose association with the thread is maintained by the operating system.
摘要翻译： 在第二不同架构的计算机上执行以第一计算机的指令集编码的程序。 操作系统维护一组并发线程中的每一个与线程上下文的一组计算机资源之间的关联。 在不修改计算机的预先存在的操作系统的情况下，将在指定的入口点或指定条件下建立要在操作系统的每个条目上提出的入口异常。 条目异常具有相关联的条目处理程序，其被编程为在将修改的上下文传送到操作系统之前，保存中断的线程的上下文并修改线程上下文。 在操作系统的每次恢复之后建立恢复异常，补充指定条目之一。 恢复异常具有相关联的退出处理程序，其被编程为恢复由相应执行的条目处理程序保存的上下文。 入口异常，退出异常，条目处理程序和退出处理程序被协调地设计为通过由操作系统引发的上下文变化来维护线程中的一个线程和线程的扩展上下文之间的关联，扩展的上下文包括 与线程相关联的计算机超出与该线程的关联的那些资源由操作系统维护。
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3.发明授权Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code 有权当执行从第一架构代码流向第二架构代码时，更改处理器的数据存储约定公开(公告)号：US08074055B1
公开(公告)日：2011-12-06
申请号：US09385394
申请日：1999-08-30
申请人： John S. Yates, Jr. , David L. Reese , Korbin S. Van Dyke , Tiruvur R. Ramesh , Paul H. Hohensee
发明人： John S. Yates, Jr. , David L. Reese , Korbin S. Van Dyke , Tiruvur R. Ramesh , Paul H. Hohensee
IPC分类号： G06F9/30
CPC分类号： G06F9/3005 , G06F9/30174 , G06F9/3804
摘要： A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline. The memory unit and/or processor pipeline recognizes an execution flow from the first page, whose associated indicator element indicates the first architecture or execution convention, to the second page, whose associated indicator element indicates the first architecture or execution convention. In response to the recognizing, a processing mode of the processor pipeline or a storage content of the memory adapts to effect execution of instructions in the architecture and/or under the convention indicated by the indicator element corresponding to the instruction's page.
摘要翻译： 一台电脑。 处理器流水线交替执行针对第一和第二不同计算机体系结构编码的编码或编码以执行第一和第二不同处理惯例的指令。 存储器存储由处理器流水线执行的指令，存储器被划分为页面以供虚拟存储器管理器管理，存储器的单个地址空间具有第一和第二页面。 存储器单元从存储器中取出指令以由流水线执行，并且获取存储的指示符元素，其与要获取指令的单个地址空间的相应存储器页相关联。 每个指示符元素被设计为存储两个不同的计算机体系结构和/或执行约定中的哪一个的指示，在该约定下，相关联的页面的指令数据将由处理器管线执行。 存储器单元和/或处理器流水线将来自第一页面的执行流程（其相关联的指示符元素指示第一架构或执行约定）识别到第二页面，其第二页面的相关联的指示符元素指示第一个架构或执行约定。 响应于识别，处理器流水线的处理模式或存储器的存储内容适应于执行由该指令页面所对应的指标元素所指示的体系结构和/或规定的指令。
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4.发明授权Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination 有权用于执行两个指令集的计算机，并添加一个宏指令结束标记，用于在循环终止后执行迭代公开(公告)号：US07941647B2
公开(公告)日：2011-05-10
申请号：US11982419
申请日：2007-10-31
IPC分类号： G06F9/22
CPC分类号： G06F9/30189 , G06F9/30174 , G06F9/30196 , G06F9/3802
摘要： A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline. The memory unit and/or processor pipeline recognizes an execution flow from the first page, whose associated indicator element indicates the first architecture or execution convention, to the second page, whose associated indicator element indicates the first architecture or execution convention. In response to the recognizing, a processing mode of the processor pipeline or a storage content of the memory adapts to effect execution of instructions in the architecture and/or under the convention indicated by the indicator element corresponding to the instruction's page.
摘要翻译： 一台电脑。 处理器流水线交替执行针对第一和第二不同计算机体系结构编码的编码或编码以执行第一和第二不同处理惯例的指令。 存储器存储由处理器流水线执行的指令，存储器被划分为页面以供虚拟存储器管理器管理，存储器的单个地址空间具有第一和第二页面。 存储器单元从存储器中取出指令以由流水线执行，并且获取存储的指示符元素，其与要获取指令的单个地址空间的相应存储器页相关联。 每个指示符元素被设计为存储两个不同的计算机体系结构和/或执行约定中的哪一个的指示，在该约定下，相关联的页面的指令数据将由处理器管线执行。 存储器单元和/或处理器流水线将来自第一页面的执行流程（其相关联的指示符元素指示第一架构或执行约定）识别到第二页面，其第二页面的相关联的指示符元素指示第一个架构或执行约定。 响应于识别，处理器流水线的处理模式或存储器的存储内容适应于执行由该指令页面所对应的指标元素所指示的体系结构和/或规定的指令。
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公开(公告)号：US07254806B1
公开(公告)日：2007-08-07
申请号：US09434394
申请日：1999-11-04
CPC分类号： G06F9/45558 , G06F9/45554 , G06F2009/45583
摘要： A computer binary translator translates at least a segment of a binary representation of a program from a first instruction set architecture to a second instruction set architecture. A sequence of side-effects in the translation differs from a sequence of side-effects in the original. The translation distinguishes memory loads that are believed to be directed to well-behaved memory from memory loads that are believed to be directed to non-well-behaved memory device(s). Instruction execution circuitry identifies a memory reference that has a side-effect that has been reordered by translation, the memory reference having been believed at translation time to be directed to well-behaved memory but at execution it is found that the reference cannot be guaranteed to be well-behaved. The instruction execution circuitry identifies whether the difference in side-effect order may have a material effect on the execution of the program. A roll-back program state is established, and execution of the original code resumes.
摘要翻译： 计算机二进制翻译器将程序的二进制表示的至少一段从第一指令集架构转换为第二指令集体系结构。 翻译中的副作用序列与原始的副作用序列不同。 该翻译区分被认为被定向到良好行为的存储器的存储器负载，这些存储器负载相信被定向到不良行为的存储器件。 指令执行电路识别具有通过转换重新排序的副作用的存储器引用，已经将翻译时间相信的存储器引用指向良好的存储器，但是在执行时，发现该引用不能被保证 表现良好。 指令执行电路识别副作用顺序的差异是否可能对程序的执行产生重大影响。 建立回滚程序状态，并恢复原始代码的执行。
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公开(公告)号：US07137110B1
公开(公告)日：2006-11-14
申请号：US09330852
申请日：1999-06-11
IPC分类号： G06F9/45
CPC分类号： G06F9/45554 , G06F9/45541 , G06F9/45558 , G06F2009/45583
摘要： Profiling execution of a program. The program is coded in a mode-dependent instruction set. During a profile-quiescent execution interval, the profile circuitry records no profile information. After a triggering event is detected, the profile circuitry commences a profiled execution interval, and records profile information describing every profileable event during that interval. The profiled information includes at least all divergence of execution from sequential execution and processor mode changes not inferable from instruction opcode. The recorded profile information is efficiently tailored to annotate the profiled binary code with sufficient processor mode information to resolve mode-dependency, and indicates contiguous ranges of sequential instructions executed during a profiled interval by low and high boundaries of the contiguous ranges, indicating the high boundary by the address of the last byte. The profile information identifies each distinct physical page of instruction text executed during the interval.
摘要翻译： 分析程序的执行。 程序以模式相关的指令集编码。 在配置文件静态执行间隔期间，配置文件电路不记录配置文件信息。 在检测到触发事件之后，简档电路开始分析执行间隔，并且记录在该间隔期间描述每个可描述事件的简档信息。 分析信息至少包括从顺序执行执行的所有分歧和处理器模式改变，不能从指令操作码推断出。 记录的配置文件信息被有效地定制以用足够的处理器模式信息来注释分布式二进制代码以解决模式依赖性，并且指示在间隔间隔期间通过连续范围的低和高边界执行的连续指令的连续范围，指示高边界 通过最后一个字节的地址。 简档信息标识在间隔期间执行的指令文本的每个不同物理页。
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7.发明授权Profiling program execution to identify frequently-executed portions and to assist binary translation 有权分析程序执行以识别经常执行的部分并协助二进制翻译公开(公告)号：US07111290B1
公开(公告)日：2006-09-19
申请号：US09425401
申请日：1999-10-22
IPC分类号： G06F9/45
CPC分类号： G06F9/45533
摘要： A method and a computer with circuitry configured for performance of the method are disclosed. During a profiled interval of an execution of a program on a computer, profile information is recorded describing the execution, without the program having been compiled for profiled execution. The program is coded in an instruction set in which an interpretation of an instruction depends on a processor mode not expressed in the binary representation of the instruction. The recorded profile information describes at least all events occurring during the profiled execution interval of the two classes: (1) a divergence of execution from sequential execution; and (2) a processor mode change that is not inferable from the opcode of the instruction that induces the processor mode change taken together with a processor mode before the mode change instruction. The profile information further identifies each distinct physical page of instruction text executed during the execution interval.
摘要翻译： 公开了一种配置用于执行该方法的电路的方法和计算机。 在计算机上执行程序的轮廓间隔期间，描述描述执行的简档信息，而没有编译用于轮廓执行的程序。 程序被编码在指令集中，其中指令的解释取决于在指令的二进制表示中未表达的处理器模式。 记录的简档信息至少描述了在两个类的分析执行间隔期间发生的所有事件：（1）执行从顺序执行的分歧; 和（2）在模式改变指令之前，与处理器模式改变一起引导处理器模式改变的处理器模式改变，其不能从引导处理器模式改变的指令的操作码推断。 简档信息进一步标识在执行间隔期间执行的指令文本的每个不同物理页。
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公开(公告)号：US06941545B1
公开(公告)日：2005-09-06
申请号：US09322443
申请日：1999-05-28
申请人： David L. Reese , John S. Yates, Jr. , Paul H. Hohensee , Korbin S. Van Dyke , T. R. Ramesh , Shalesh Thusoo , Gurjeet Singh Saund , Niteen Aravind Patkar
发明人： David L. Reese , John S. Yates, Jr. , Paul H. Hohensee , Korbin S. Van Dyke , T. R. Ramesh , Shalesh Thusoo , Gurjeet Singh Saund , Niteen Aravind Patkar
CPC分类号： G06F9/45554 , G06F9/45541 , G06F9/45558 , G06F2009/45583
摘要： A computer. An instruction pipeline and memory access unit execute instructions in a logical address space of a memory of the computer. An address translation circuit translates address references generated by the program from the program's logical address space to the computer's physical address space. Profile circuitry is cooperatively interconnected with the instruction pipeline and configured to detect, without compiler assistance for execution profiling, occurrence of profilable events occurring in the instruction pipeline, and is cooperatively interconnected with the memory access unit to record profile information describing physical memory addresses referenced during an execution interval of the program.
摘要翻译： 一台电脑。 指令流水线和存储器访问单元在计算机的存储器的逻辑地址空间中执行指令。 地址转换电路将由程序生成的地址参考从程序的逻辑地址空间转换为计算机的物理地址空间。 简档电路与指令流水线协作地互连，并且被配置为在没有编译器帮助执行分析的情况下检测在指令流水线中发生的可概要事件的发生，并且与存储器访问单元协作地互连以记录描述参考的物理存储器地址的简档信息 程序的执行间隔。
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9.发明授权Recording in a program execution profile references to a memory-mapped active device 有权在程序执行配置文件中记录引用存储器映射的活动设备公开(公告)号：US06397379B1
公开(公告)日：2002-05-28
申请号：US09428850
申请日：1999-10-28
IPC分类号： G06F944
CPC分类号： G06F9/45554 , G06F9/45558 , G06F2009/45579 , G06F2009/45583
摘要： A method and a computer for execution of the method. As part of executing a stream of instructions, a series of memory loads is issued from a computer CPU to a bus, some directed to well-behaved memory and some directed to non-well-behaved devices in I/O space. Computer addresses are stored of instructions of the stream that issued memory loads to the non-well-behaved memory, the storage form of the recording allowing determination of whether the memory load was to well-behaved memory or not-well-behaved memory without resolution of any memory address stored in the recording.
摘要翻译： 用于执行该方法的方法和计算机。 作为执行指令流的一部分，从计算机CPU向总线发出一系列内存负载，一些针对良好的内存，一些定向到I / O空间中不良的设备。 计算机地址存储了将内存负载发送到不良行为的存储器的流的指令，记录的存储形式允许确定存储器负载是否表现良好的存储器还是不具有良好的存储器而没有解决 存储在记录中的任何存储器地址。
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10.发明授权Apparatus for executing instruction regardless of data types and thereafter selectively branching to other instruction upon determining of incompatible data type 失效用于执行指令而不管数据类型，然后在确定不兼容的数据类型时选择性地分支到其他指令的装置
公开(公告)号：US5045992A
公开(公告)日：1991-09-03
申请号：US259792
申请日：1988-10-19
CPC分类号： G06F9/30192 , G06F8/312 , G06F9/3889
摘要： A method and apparatus for improving the efficiency of executing arithmetic and logical operations performed on arguments provided during the execution of computer instructions in which operands include a variable type argument or data portion accompanied by a tag identifier which defines the data type. The processing of the data is enhanced by the addition of two condition codes derived from the values of the pre-ALU tag identifiers and the post-ALU results. The condition codes allow rapid determination of data types without additional execution cycles or hardware overhead, resulting in enhanced execution of the instructions.
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