公开(公告)号：US06517235B2

公开(公告)日：2003-02-11

申请号：US09867560

申请日：2001-05-31

申请人： Zhong Yun Zhu ,  Rajneesh Jaiswal ,  Haznita Abd Karim ,  Bei Chao Zhang ,  Johnny Cham ,  Ravi Sankar Yelamanchi ,  Chee Kong Leong

发明人： Zhong Yun Zhu ,  Rajneesh Jaiswal ,  Haznita Abd Karim ,  Bei Chao Zhang ,  Johnny Cham ,  Ravi Sankar Yelamanchi ,  Chee Kong Leong

IPC分类号： G01K1700

CPC分类号： G01K15/002

摘要： A method for controlling and/or calibrating rapid thermal process systems is described. One or more wafers comprising a silicon semiconductor substrate having a refractory metal layer thereon are silicided in a RTP system at different temperatures. Sheet resistance uniformity of the wafer is measured thereby detecting silicidation phase transition temperature points at the highest uniformity points. The temperature points are used to calibrate or to reset the RTP system. A plurality of wafers comprising a silicon semiconductor substrate having a refractory metal layer thereon can be silicided in each of a plurality of rapid thermal process systems. Sheet resistance uniformity of each of the wafers is measured thereby detecting silicidation phase transition temperature points by highest sheet resistance uniformity for each of the RTP systems. The temperature points are used to match temperatures for each of the RTP systems. The temperature point depend upon the type of refractory metal used and can range from about 200 to 800 ° C.

摘要翻译： 描述了用于控制和/或校准快速热处理系统的方法。 包括其上具有难熔金属层的硅半导体衬底的一个或多个晶片在不同温度的RTP系统中被硅化。 测量晶片的片电阻均匀性，从而检测最高均匀点处的硅化相变温度点。 温度点用于校准或复位RTP系统。 包括其上具有难熔金属层的硅半导体衬底的多个晶片可以在多个快速热处理系统中的每一个中被硅化。 测量每个晶片的薄片电阻均匀性，从而通过每个RTP系统的最高薄层电阻均匀性来检测硅化相变温度点。 温度点用于匹配每个RTP系统的温度。 温度点取决于使用的难熔金属的类型，可以在约200至800℃的范围内

公开(公告)号：US06701199B1

公开(公告)日：2004-03-02

申请号：US10225804

申请日：2002-08-22

申请人： Cheng Chor Shu ,  Cho Nam Hoon ,  Leong Chee Kong ,  Pete Benyon ,  Johnny Cham ,  George Wong ,  Neoh Soon Ee

发明人： Cheng Chor Shu ,  Cho Nam Hoon ,  Leong Chee Kong ,  Pete Benyon ,  Johnny Cham ,  George Wong ,  Neoh Soon Ee

IPC分类号： G06F1900

CPC分类号： G05B19/4188 ,  H01L21/67276 ,  Y02P90/24 ,  Y02P90/26

摘要： In accordance with the objectives of the invention a new methodology is provided that assures that integrated process results are verified and assured prior to the installation of processing tools as part of modifying or updating of a semiconductor manufacturing foundry. The complete semiconductor manufacturing complement of processing tools is sub-divided into short-loops or sub-modules, which are then combined into a full loop. This combination of sub-modules into modules that closer approach a full complement of processing tools can be accomplished in a gradual manner, whereby one or more sub-loops are first combined and evaluated, to this combination one or more additional sub-groups may be added whereby each of these latter sub-groups may also have been created by combining one or more (original) sub-loops. This process is continued to the point where a full complement of process equipment has been created, completing the full processing loops of the semiconductor manufacturing facility.

摘要翻译： 根据本发明的目的，提供了一种新的方法，其确保在作为修改或更新半导体制造代工厂的一部分之前，在安装处理工具之前验证并确保综合的处理结果。 加工工具的完整半导体制造补充被分为短环或子模块，然后将其组合成一个完整的循环。 将子模块组合成更接近整个处理工具的模块的组合可以以逐步的方式完成，由此首先将一个或多个子回路组合和评估到该组合中，一个或多个附加子组可以是 其中这些后一子组中的每一个也可以通过组合一个或多个（原始）子回路而创建。 这个过程继续到已经完成了完整的工艺设备的创建，完成了半导体制造设备的完整处理循环。