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公开(公告)号：US20080248599A1
公开(公告)日：2008-10-09
申请号：US12142625
申请日：2008-06-19
IPC分类号： H01L21/00
摘要： A method of determining the degree of calibration of an RTP chamber (1) includes providing a test wafer having a deposited sichrome layer (22) of sheet resistance Rsi on an oxide layer (21) formed on a silicon substrate (20). The test wafer is annealed in the RTP chamber for a selected duration at a selected anneal temperature which is measured by the a permanent thermocouple or pyrometer (8). The sheet resistance of the annealed sichrome is measured, and a sheet resistance change Rs=Rsi−Rsf is computed. The “actual” value of the anneal temperature is determined from predetermined characterizing information relating Rs to a range of values of anneal temperature. The RTP chamber is re-calibrated if in accordance with the value of Rs if the difference between the “actual” value of the anneal temperature and the value measured by the permanent thermocouple or pyrometer exceeds an acceptable error. The basic technique can be utilized to determine an anneal time and anneal duration for annealing sichrome resistors to precisely adjust the sheet resistance or TCR thereof.
摘要翻译： 确定RTP室（1）的校准程度的方法包括在形成在硅衬底（20）上的氧化物层（21）上提供具有片状电阻Rsi的沉积的铬酸盐层（22）的测试晶片。 测试晶片在RTP室中以选定的退火温度退火一段选定的退火温度，该退火温度由永久热电偶或高温计（8）测量。 测量退火的三色铬的薄层电阻，计算薄层电阻变化Rs = Rsi-Rsf。 退火温度的“实际”值由将退火温度的值的范围内的Rs相关的规定的特征信息求出。 如果退火温度的“实际”值与由永久热电偶或高温计测量的值之间的差异超过了可接受的误差，则根据Rs的值重新校准RTP室。 可以利用基本技术来确定退火时间和退火持续时间，以精确调整薄膜电阻或TCR。
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公开(公告)号：US07354854B2
公开(公告)日：2008-04-08
申请号：US11136159
申请日：2005-05-24
申请人： Rajneesh Jaiswal
发明人： Rajneesh Jaiswal
IPC分类号： H01L21/4763
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/78
摘要： Nickel silicide contact regions are formed on a source (2), drain (3) and polycrystalline silicon gate (5) of an integrated circuit transistor by annealing it after a nickel layer has been deposited on the source, drain, and gate, with no cap layer on the nickel layer. Nickel silicide bridging between the gate and source and/or drain is avoided or eliminated by using a chrome etching process to remove un-reacted nickel and nickel remnants from exposed surfaces of dielectric spacers (6A,B) located between the gate and source and between the gate and drain. The chrome etching process includes use of a solution including cerric ammonium nitrate, nitric acid, and acetic acid.
摘要翻译： 硅化镍接触区域在集成电路晶体管的源极（2），漏极（3）和多晶硅栅极（5）上形成在镍层已经沉积在源极，漏极和栅极上之后通过退火而没有 盖层在镍层上。 通过使用铬蚀刻工艺从位于栅极和源极之间的介电间隔物（6A，B）的暴露表面去除未反应的镍和镍残余物来避免或消除栅极和源极和/或漏极之间的硅化镍桥接，以及 在闸门和排水沟之间。 铬蚀刻工艺包括使用包括硝酸铵铵，硝酸和乙酸的溶液。
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公开(公告)号：US06734076B1
公开(公告)日：2004-05-11
申请号：US10390054
申请日：2003-03-17
申请人： Rajneesh Jaiswal , Eric W. Beach
发明人： Rajneesh Jaiswal , Eric W. Beach
IPC分类号： H01L2120
CPC分类号： H01L28/20 , H01L21/768 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： A thin film resistor (55) is formed over an etch stop layer 40. Contact pads (65) are formed n the thin film resistor (55) and a dielectric layer (80) is formed over the thin film resistor (55). Metal structures (120 are formed above the thin film resistor (55) and metal (110) is used to fill a trench and via formed in the dielectric layer (80).
摘要翻译： 薄膜电阻器（55）形成在蚀刻停止层40上方。在薄膜电阻器（55）上形成接触焊盘（65），并在薄膜电阻器（55）之上形成介电层（80）。 金属结构（120）形成在薄膜电阻器（55）上方，并且金属（110）用于填充在电介质层（80）中形成的沟槽和通孔。
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公开(公告)号：US07323751B2
公开(公告)日：2008-01-29
申请号：US10453701
申请日：2003-06-03
IPC分类号： H01L29/72
CPC分类号： H01L23/5226 , H01L23/5228 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： A thin film resistor and at least one metal interconnect are formed in an integrated circuit. A first dielectric layer is formed over a metal interconnect layer. A thin film resistor is formed on the first dielectric layer and a second dielectric layer formed over the thin film resistor. Thin film resistor vias and the at least one trench are formed concurrently in the second dielectric layer. A trench via is then formed in the at least one trench. The trench via, the at least one trench and the thin film resistor vias are filled with a contact material layer to form thin film resistor contacts and at least one conductive line coupled to the metal interconnect layer.
摘要翻译： 在集成电路中形成薄膜电阻器和至少一个金属互连。 在金属互连层上形成第一介电层。 在第一电介质层上形成薄膜电阻，在薄膜电阻上形成第二电介质层。 在第二电介质层中同时形成薄膜电阻器通孔和至少一个沟槽。 然后在至少一个沟槽中形成沟槽通孔。 沟槽通孔，至少一个沟槽和薄膜电阻器通孔填充有接触材料层，以形成薄膜电阻器触点和耦合到金属互连层的至少一个导线。
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公开(公告)号：US07196398B2
公开(公告)日：2007-03-27
申请号：US11071908
申请日：2005-03-04
IPC分类号： H01L29/00
摘要： A method of preventing contact noise in a SiCr thin film resistor includes performing in situ depositions of a SiCr layer and then a TiW layer on a substrate without breaking a vacuum between the depositions, to prevent formation of any discontinuous oxide between the SiCr layer and the TiW layer. The SiCr and TiW layers are patterned to form a predetermined SiCr thin film resistor pattern and a TiW resistor contact pattern on the SiCr thin film resistor, and a metallization layer is provided to contact the TiW forming the resistor contact pattern.
摘要翻译： 防止SiCr薄膜电阻中的接触噪声的方法包括在基板上进行SiCr层和TiW层的原位沉积，而不破坏沉积物之间的真空，以防止在SiCr层与SiCr层之间形成任何不连续的氧化物 TiW层。 将SiCr和TiW层图案化以在SiCr薄膜电阻器上形成预定的SiCr薄膜电阻器图案和TiW电阻器接触图案，并且提供金属化层以接触形成电阻器接触图案的TiW。
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6.发明授权公开(公告)号：US06517235B2
公开(公告)日：2003-02-11
申请号：US09867560
申请日：2001-05-31
申请人： Zhong Yun Zhu , Rajneesh Jaiswal , Haznita Abd Karim , Bei Chao Zhang , Johnny Cham , Ravi Sankar Yelamanchi , Chee Kong Leong
发明人： Zhong Yun Zhu , Rajneesh Jaiswal , Haznita Abd Karim , Bei Chao Zhang , Johnny Cham , Ravi Sankar Yelamanchi , Chee Kong Leong
IPC分类号： G01K1700
CPC分类号： G01K15/002
摘要： A method for controlling and/or calibrating rapid thermal process systems is described. One or more wafers comprising a silicon semiconductor substrate having a refractory metal layer thereon are silicided in a RTP system at different temperatures. Sheet resistance uniformity of the wafer is measured thereby detecting silicidation phase transition temperature points at the highest uniformity points. The temperature points are used to calibrate or to reset the RTP system. A plurality of wafers comprising a silicon semiconductor substrate having a refractory metal layer thereon can be silicided in each of a plurality of rapid thermal process systems. Sheet resistance uniformity of each of the wafers is measured thereby detecting silicidation phase transition temperature points by highest sheet resistance uniformity for each of the RTP systems. The temperature points are used to match temperatures for each of the RTP systems. The temperature point depend upon the type of refractory metal used and can range from about 200 to 800 ° C.
摘要翻译： 描述了用于控制和/或校准快速热处理系统的方法。 包括其上具有难熔金属层的硅半导体衬底的一个或多个晶片在不同温度的RTP系统中被硅化。 测量晶片的片电阻均匀性，从而检测最高均匀点处的硅化相变温度点。 温度点用于校准或复位RTP系统。 包括其上具有难熔金属层的硅半导体衬底的多个晶片可以在多个快速热处理系统中的每一个中被硅化。 测量每个晶片的薄片电阻均匀性，从而通过每个RTP系统的最高薄层电阻均匀性来检测硅化相变温度点。 温度点用于匹配每个RTP系统的温度。 温度点取决于使用的难熔金属的类型，可以在约200至800℃的范围内
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公开(公告)号：US07384855B2
公开(公告)日：2008-06-10
申请号：US11553270
申请日：2006-10-26
IPC分类号： H01L21/20
摘要： A method of preventing contact noise in a SiCr thin film resistor includes performing in situ depositions of a SiCr layer and then a TiW layer on a substrate without breaking a vacuum between the depositions, to prevent formation of any discontinuous oxide between the SiCr layer and the TiW layer. The SiCr and TiW layers are patterned to form a predetermined SiCr thin film resistor pattern and a TiW resistor contact pattern on the SiCr thin film resistor, and a metallization layer is provided to contact the TiW forming the resistor contact pattern.
摘要翻译： 防止SiCr薄膜电阻中的接触噪声的方法包括在基板上进行SiCr层和TiW层的原位沉积，而不破坏沉积物之间的真空，以防止在SiCr层与SiCr层之间形成任何不连续的氧化物 TiW层。 将SiCr和TiW层图案化以在SiCr薄膜电阻器上形成预定的SiCr薄膜电阻器图案和TiW电阻器接触图案，并且提供金属化层以接触形成电阻器接触图案的TiW。
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8.发明授权Use of a biased precoat for reduced first wafer defects in high-density plasma process 有权在高密度等离子体工艺中使用偏压预涂层来减少第一晶圆缺陷公开(公告)号：US07964517B2
公开(公告)日：2011-06-21
申请号：US12362320
申请日：2009-01-29
申请人： Rajneesh Jaiswal
发明人： Rajneesh Jaiswal
IPC分类号： H01L21/31
CPC分类号： H01L21/31604 , C23C16/4404 , C23C16/505
摘要： According to various embodiments, the present teachings include methods for reducing first wafer defects in a high-density plasma chemical vapor deposition process. In an exemplary embodiment, the method can include running a deposition chamber for deposition of film on a first batch of silicon wafers and then cleaning interior surfaces of the deposition chamber. The method can further include inserting a protective electrostatic chuck cover (PEC) wafer on an electrostatic chuck in the deposition chamber and applying power to bias the PEC wafer while simultaneously precoating the deposition chamber with an oxide. The exemplary method can also include re-starting the deposition chamber for deposition of film on a second batch of silicon wafers.
摘要翻译： 根据各种实施例，本教导包括用于减少高密度等离子体化学气相沉积工艺中的第一晶片缺陷的方法。 在示例性实施例中，该方法可以包括运行沉积室，用于在第一批硅晶片上沉积膜，然后清洁沉积室的内表面。 该方法还可以包括将保护性静电卡盘盖（PEC）晶片插入到沉积室中的静电卡盘上，并施加电力以偏压PEC晶片，同时用氧化物预涂镀层。 示例性方法还可以包括重新开始用于在第二批硅晶片上沉积膜的沉积室。
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9.发明申请USE OF A BIASED PRECOAT FOR REDUCED FIRST WAFER DEFECTS IN HIGH-DENSITY PLASMA PROCESS 有权在高密度等离子体过程中减少第一波形缺陷的偏置预处理的使用公开(公告)号：US20100190352A1
公开(公告)日：2010-07-29
申请号：US12362320
申请日：2009-01-29
申请人： Rajneesh JAISWAL
发明人： Rajneesh JAISWAL
CPC分类号： H01L21/31604 , C23C16/4404 , C23C16/505
摘要： According to various embodiments, the present teachings include methods for reducing first wafer defects in a high-density plasma chemical vapor deposition process. In an exemplary embodiment, the method can include running a deposition chamber for deposition of film on a first batch of silicon wafers and then cleaning interior surfaces of the deposition chamber. The method can further include inserting a protective electrostatic chuck cover (PEC) wafer on an electrostatic chuck in the deposition chamber and applying power to bias the PEC wafer while simultaneously precoating the deposition chamber with an oxide. The exemplary method can also include re-starting the deposition chamber for deposition of film on a second batch of silicon wafers.
摘要翻译： 根据各种实施例，本教导包括用于减少高密度等离子体化学气相沉积工艺中的第一晶片缺陷的方法。 在示例性实施例中，该方法可以包括运行沉积室，用于在第一批硅晶片上沉积膜，然后清洁沉积室的内表面。 该方法还可以包括将保护性静电卡盘盖（PEC）晶片插入到沉积室中的静电卡盘上，并施加电力以偏压PEC晶片，同时用氧化物预涂镀层。 示例性方法还可以包括重新开始用于在第二批硅晶片上沉积膜的沉积室。
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10.发明申请公开(公告)号：US20100167552A1
公开(公告)日：2010-07-01
申请号：US12345732
申请日：2008-12-30
CPC分类号： H01L21/02063 , H01L21/67051 , H01L21/67109
摘要： A method of manufacturing an IC device includes providing a workpiece having least one dielectric layer disposed on a surface of the workpiece. The method also includes processing the dielectric layer to form a plurality of apertures in the dielectric layer, where the processing includes at least one micromask-prone process. The method further includes subsequent to the processing step, cryogenically treating the workpiece. In the method, the treating step removes particles deposited on or in the plurality of apertures during the processing step and maintains the plurality of apertures, where the particles are generated from micromask features resulting from the micromask-prone process.
摘要翻译： 制造IC器件的方法包括提供具有设置在工件表面上的至少一个电介质层的工件。 该方法还包括处理电介质层以在电介质层中形成多个孔，其中该处理包括至少一个易于微成像的方法。 该方法还包括在处理步骤之后，对工件进行低温处理。 在该方法中，处理步骤除去在处理步骤期间沉积在多个孔中或在多个孔中的颗粒，并维持多个孔，其中颗粒是由微阵列易位过程产生的微掩模特征产生的。
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