公开(公告)号：US5060054A

公开(公告)日：1991-10-22

申请号：US278501

申请日：1988-12-01

申请人： Joji Murakami ,  Minoru Wano

发明人： Joji Murakami ,  Minoru Wano

IPC分类号： H04N9/00 ,  G09G1/00 ,  G09G5/00 ,  G09G5/04 ,  G09G5/18 ,  H04N9/16 ,  H04N9/64 ,  H04N9/68

CPC分类号： H04N9/68 ,  H04N9/64

摘要： A device for controlling a color video display which includes ladder resistor units having a plurality of taps; a clock signal generating unit for generating four-phase clock signals having the same frequency as the frequency of a sub-carrier from a clock signal having a frequency which is four times the frequency of the sub-carrier, and a color signal generating unit for receiving data corresponding to colors to be displayed and for generating color signals, by successively selecting taps of the ladder resistor units corresponding to the colors to be displayed, in synchronization with the four-phase clock signals. The generation of color signals having a precise phase angle relationships are ensured by this device.

公开(公告)号：US5001629A

公开(公告)日：1991-03-19

申请号：US110725

申请日：1987-09-25

申请人： Joji Murakami ,  Kenji Yamada ,  Hideki Isobe ,  Toshiyuki Igarashi ,  Yoshihiro Kubo

发明人： Joji Murakami ,  Kenji Yamada ,  Hideki Isobe ,  Toshiyuki Igarashi ,  Yoshihiro Kubo

IPC分类号： G06F9/30 ,  G06F9/312

CPC分类号： G06F9/30043

摘要： In a central processing unit, one write address is made to correspond to a pair of registers, and when an instruction output from an instruction decoder is a data transfer instruction to either one of the above-mentioned pair of registers, the data held in one of the above-mentioned pair of registers is kept to be held in either register of the above-mentioned pair of registers and the data from the internal data bus is transferred to the remaining register of the pair of registers, and in response to a read instruction, data is transferred from each register to the internal data bus without changing the contents of the other register.

公开(公告)号：US4841298A

公开(公告)日：1989-06-20

申请号：US132441

申请日：1987-12-14

申请人： Joji Murakami ,  Syogo Sibazaki ,  Junya Tempaku

发明人： Joji Murakami ,  Syogo Sibazaki ,  Junya Tempaku

IPC分类号： G06F3/14 ,  G06F7/76

CPC分类号： G06F7/768 ,  G06F3/14

摘要： A bit pattern conversion system for converting a sequence of a bit pattern between a central processing unit and a peripheral circuit, including a data bus line connected between the central processing unit and the peripheral circuit, and a conversion circuit provided in the peripheral circuit for converting the sequence of the bit pattern from a most significant bit to a least significant bit, and vice versa, in accordance with a conversion signal.

公开(公告)号：US06980977B2

公开(公告)日：2005-12-27

申请号：US10007887

申请日：2001-11-05

申请人： Tetsuo Hoshi ,  Joji Murakami ,  Masahiro Ibaragi ,  Kazuya Kubo ,  Jun Murai ,  Masaki Minami ,  Takeo Kuwabara ,  Masaaki Yonezawa ,  Tsutomu Sano

发明人： Tetsuo Hoshi ,  Joji Murakami ,  Masahiro Ibaragi ,  Kazuya Kubo ,  Jun Murai ,  Masaki Minami ,  Takeo Kuwabara ,  Masaaki Yonezawa ,  Tsutomu Sano

IPC分类号： G06F17/30 ,  H04H20/00 ,  G06F7/00

CPC分类号： G06F17/30867 ,  Y10S707/99931 ,  Y10S707/99935

摘要： An information delivery system having a service section; a plurality of nodes connected to the service section through a network and allocated with specific addresses that are unique within the network; and terminal devices for system users connected to the service section and the plurality of nodes through the network; wherein the service section acquires profile data of each node user through each node and analyzes the person profile data in order to mediate between each node user and each system user according to the profile data to help exchange information.

摘要翻译： 一种具有服务部分的信息传递系统; 多个节点通过网络连接到服务部分并且分配具有在网络内唯一的特定地址; 以及通过网络连接到服务部分和多个节点的系统用户的终端设备; 其中所述服务部分通过每个节点获取每个节点用户的简档数据，并且根据所述简档数据分析所述人员简档数据以便在每个节点用户和每个系统用户之间进行调停以帮助交换信息。

公开(公告)号：US4604692A

公开(公告)日：1986-08-05

申请号：US454258

申请日：1982-12-29

申请人： Joji Murakami

发明人： Joji Murakami

IPC分类号： G06F3/023 ,  G01R31/317 ,  G06F1/00 ,  G06F1/24 ,  G06F3/05 ,  G06F9/30 ,  G06F15/78 ,  H03M11/14 ,  G06F3/00

CPC分类号： G06F1/24 ,  G01R31/31701 ,  G06F1/00 ,  G06F3/05

摘要： An operation mode setting system is provided in a microprocessor operable in a plurality of operation modes. The operation mode setting system has a signal input line through which an analog voltage corresponding to any of the respective operation modes is applied to an analog-to-digital converter circuit which is built in the microprocessor. The output signal from the analog-to-digital converter circuit is decoded by a decoder, and the microprocessor is set at the predetermined operation mode in response to the decoded output signal.

摘要翻译： 在可操作于多种操作模式的微处理器中提供操作模式设置系统。 操作模式设置系统具有信号输入线，通过该信号输入线将对应于任一相应操作模式的模拟电压施加到内置在微处理器中的模数转换器电路。 来自模数转换器电路的输出信号由解码器解码，并且响应于解码的输出信号将微处理器设置在预定的操作模式。