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公开(公告)号：US5608897A
公开(公告)日：1997-03-04
申请号：US667767
申请日：1996-06-21
IPC分类号： G06F1/14
CPC分类号： G06F1/14
摘要： A timeout mechanism for a computer system is provided, comprising a clocked linear feedback shift register and a programmable comparing mechanism. The linear feedback shift register comprises a series of latches serially connected to each other, and is responsive to a received interrupt signal to (i) incrementally count sequentially in the presence of the interrupt signal to provide a distinct binary vector array at the outputs of the latches for each count in the sequence and (ii) reset to a particular binary vector array in the absence of the interrupt signal. The comparing mechanism outputs a timeout command in response to the linear feedback shift register reaching a predetermined count and outputting a corresponding predetermined binary vector array at the output of the latches. The timeout mechanism uses a minimal amount of combinatorial logic, while permitting the issuance of a timeout command after the detection of an interrupt signal after any multiple of clock cycles.
摘要翻译： 提供了一种用于计算机系统的超时机制，包括时钟线性反馈移位寄存器和可编程比较机制。 线性反馈移位寄存器包括串联连接的一系列锁存器，并且响应于接收到的中断信号（i）在存在中断信号的情况下依次增量地计数，以在中断信号的输出端提供不同的二进制向量阵列 按序列中的每个计数锁存，以及（ii）在不存在中断信号的情况下复位到特定的二进制向量阵列。 比较机构响应于线性反馈移位寄存器输出预定计数并在锁存器的输出处输出相应的预定二进制向量阵列来输出超时命令。 超时机制使用最小量的组合逻辑，同时允许在任何多个时钟周期之后检测到中断信号后发出超时命令。
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2.发明授权Boundary-scan bypass circuit for integrated circuit electronic component and circuit boards incorporating such circuits and components 失效用于集成电路电子元件的边界扫描旁路电路和包含这样的电路和部件的电路板
公开(公告)号：US5615217A
公开(公告)日：1997-03-25
申请号：US352080
申请日：1994-12-01
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318558
摘要： A method and apparatus for bypassing a boundary-scan cell during functional operation of an electronic component provides a component output signal (such as a data signal) to a boundary-scan bypass circuit during normal functional operation of the electronic component. The component output signal is multiplexed in the bypass circuit with the test result signal that occurs during boundary-scan testing. During functional operation of the electronic component, the component output signal is selected and provided to an output latch that is clocked by a transition of the clock signal of the electronic component. By bypassing the component output signal around the boundary-scan cell during normal operation, the traversing of the multiplexer by the component output signal after the transition of the clock signal of the component is avoided, thereby reducing off-chip delay.
摘要翻译： 一种用于在电子部件的功能操作期间旁路边界扫描单元的方法和装置在电子部件的正常功能操作期间向边界扫描旁路电路提供分量输出信号（例如数据信号）。 分量输出信号在旁路电路中被复用在边界扫描测试期间发生的测试结果信号。 在电子部件的功能操作期间，分量输出信号被选择并提供给由电子部件的时钟信号的转变而被定时的输出锁存器。 通过在正常操作期间绕过边界扫描单元周围的分量输出信号，避免了在分量的时钟信号转变之后通过分量输出信号的多路复用器的遍历，从而减少了片外延迟。
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3.发明授权Computer system and method with integrated level and edge interrupt requests at the same interrupt priority 失效具有相同中断优先级的集成级和边缘中断请求的计算机系统和方法
公开(公告)号：US5555413A
公开(公告)日：1996-09-10
申请号：US390610
申请日：1995-02-17
申请人： Terence Lohman , Mark G. Noll , Jose A. Olive , Roberto V. Perez
发明人： Terence Lohman , Mark G. Noll , Jose A. Olive , Roberto V. Perez
CPC分类号： G06F9/4812
摘要： A computer system that has a processor that services interrupts in response to receipt of a signal at the interrupt request has a first device and a second device coupled to the processor. The first device is capable of transmitting a first interrupt request signal that includes an edge transition. The second device is capable of transmitting a second interrupt request signal that comprises a level assertion. An interrupt handler is coupled to the processor and the first and second devices, the interrupt handler receiving the first and second interrupt request signals as inputs and providing the first and second interrupt request signals as outputs to the processor in a sequence according to a predetermined criteria, the first and second interrupt request signals having identical priority.
摘要翻译： 具有响应于在中断请求处接收到信号而服务中断的处理器的计算机系统具有耦合到处理器的第一设备和第二设备。 第一设备能够发送包括边缘转换的第一中断请求信号。 第二设备能够发送包括电平断言的第二中断请求信号。 中断处理程序耦合到处理器和第一和第二设备，中断处理程序接收第一和第二中断请求信号作为输入，并且根据预定标准将处理器的第一和第二中断请求信号作为输出提供给处理器 第一和第二中断请求信号具有相同的优先级。
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4.发明授权Computer system having a selectable memory module presence detect information option 失效具有可选存储器模块存在检测信息选项的计算机系统
公开(公告)号：US5539912A
公开(公告)日：1996-07-23
申请号：US279308
申请日：1994-07-22
CPC分类号： G06F13/4243 , G06F12/0684
摘要： A personal computer has two possible memory sizes differing by the maximum number SIMMs that can be installed. Each SIMM stores presence detect bits indicating the size and speed of the SIMM. An I/O controller includes a memory detect port which is used to read the presence detect bits from the SIMMs. The controller further includes a logic circuit that is set in accordance with the memory size to selectively control driving the presence detect bits or empty socket bits onto a data bus.
摘要翻译： 个人计算机有两种可能的存储容量大小，可以通过最大数量的SIMM来安装。 每个SIMM存储指示SIMM的大小和速度的存在检测位。 I / O控制器包括用于从SIMM读取存在检测位的存储器检测端口。 控制器还包括根据存储器大小设置的逻辑电路，以选择性地控制将存在检测位或空插座位驱动到数据总线上。
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公开(公告)号：US5544334A
公开(公告)日：1996-08-06
申请号：US172124
申请日：1993-12-22
申请人： Mark G. Noll
发明人： Mark G. Noll
CPC分类号： G06F13/404
摘要： A computer system having: a central processing unit (CPU), having a system bus associated therewith, a first bus interface circuit (BIC) in circuit communication with the CPU and generating a peripheral bus, such as the MICRO CHANNEL bus, a floppy drive controller (FDC), and an Integrated Drive Electronics (IDE) hardfile (hard drive). The IDE hardfile is in electrical circuit communication with the peripheral bus via a second bus interface circuit. The second bus interface circuit includes a writable latch having at least two states and in circuit communication with the peripheral bus. The latch states are selectable by the CPU via the system bus. The second bus interface circuit also has an access control circuit in circuit communication with the peripheral bus, the system bus, and the latch for selectively allowing data transfers between the CPU and either the FDC or the IDE hard drive, depending on the state of the latch.
摘要翻译： 一种计算机系统，其具有：具有与其相关联的系统总线的中央处理单元（CPU），与CPU电路通信的第一总线接口电路（BIC），并产生诸如MICRO CHANNEL总线的外围总线，软盘驱动器 控制器（FDC）和集成驱动电子（IDE）硬盘（硬盘驱动器）。 IDE硬盘通过第二总线接口电路与外围总线进行电路通信。 第二总线接口电路包括具有至少两个状态并与外围总线进行电路通信的可写锁存器。 锁存状态由CPU通过系统总线选择。 第二总线接口电路还具有与外围总线，系统总线和锁存器进行电路通信的访问控制电路，用于选择性地允许CPU与FDC或IDE硬盘驱动器之间的数据传输，这取决于 锁定。
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公开(公告)号：US08875280B2
公开(公告)日：2014-10-28
申请号：US13273638
申请日：2011-10-14
IPC分类号： G06F21/00
摘要： Embodiments of the present invention provide an approach for protecting electronic devices against the use of unqualified and/or unauthorized (e.g., “grey market”) hardware components. Specifically, in a typical embodiment, a hardware component that a user is attempting to use with an electronic device will be detected. Then, the device information associated with the hardware component (e.g., serial number, vital product data (VPD), etc.) will be identified from the hardware component (e.g., as stored therein).
摘要翻译： 本发明的实施例提供了一种用于保护电子设备免受不合格和/或未授权（例如“灰色市场”）硬件组件的使用的方法。 具体地说，在典型的实施例中，将检测用户试图与电子设备一起使用的硬件组件。 然后，将从硬件组件（例如，存储在其中）识别与硬件组件（例如，序列号，重要产品数据（VPD）等）相关联的设备信息。
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公开(公告)号：US20130097694A1
公开(公告)日：2013-04-18
申请号：US13273638
申请日：2011-10-14
IPC分类号： G06F21/00
摘要： Embodiments of the present invention provide an approach for protecting electronic devices against the use of unqualified and/or unauthorized (e.g., “grey market”) hardware components. Specifically, in a typical embodiment, a hardware component that a user is attempting to use with an electronic device will be detected. Then, the device information associated with the hardware component (e.g., serial number, vital product data (VPD), etc.) will be identified from the hardware component (e.g., as stored therein).
摘要翻译： 本发明的实施例提供了一种用于保护电子设备免受不合格和/或未授权（例如“灰色市场”）硬件组件的使用的方法。 具体地说，在典型的实施例中，将检测用户试图与电子设备一起使用的硬件组件。 然后，将从硬件组件（例如，存储在其中）识别与硬件组件（例如，序列号，重要产品数据（VPD）等）相关联的设备信息。
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