公开(公告)号：US06774942B1

公开(公告)日：2004-08-10

申请号：US09642613

申请日：2000-08-17

Applicant: Jose A. Salcedo ,  Srinivas N. Neti ,  Charles A. Rogers

Inventor： Jose A. Salcedo ,  Srinivas N. Neti ,  Charles A. Rogers

IPC: H04N964

CPC classification number: H04N5/361

Abstract: An improved offset correction circuit for an image digitizing system having a correlated double sample and hold circuit, a programmable gain amplifier and an analog-to-digital converter. The output of the analog-to-digital converter is provided to a dual offset correction circuit. The dual offset correction circuit provides both first and second correction values as feedback signals. In one embodiment, the first correction value is a coarse correction which is applied prior to amplification by the programmable gain amplifier. The second correction value is a fine correction offset which is applied as feedback after the programmable gain amplifier.

Abstract translation: 一种用于具有相关双采样和保持电路的图像数字化系统的改进的偏移校正电路，可编程增益放大器和模数转换器。 模数转换器的输出被提供给双偏移校正电路。 双偏移校正电路提供第一和第二校正值作为反馈信号。 在一个实施例中，第一校正值是在可编程增益放大器放大之前应用的粗略校正。 第二校正值是在可编程增益放大器之后用作反馈的精细校正偏移。

公开(公告)号：US06340944B1

公开(公告)日：2002-01-22

申请号：US09643385

申请日：2000-08-21

Applicant: Ronald Chang ,  Jose A. Salcedo ,  Raphael Horton

Inventor： Ronald Chang ,  Jose A. Salcedo ,  Raphael Horton

IPC: H03M144

CPC classification number: H03M1/002 ,  H03M1/168 ,  H03M1/44

Abstract: An analog-to-digital converter which has a low resolution and high resolution mode. In response to the low resolution mode signal, a switching circuit selects only certain of the digital bit outputs. In one embodiment, the analog-to-digital converter is a pipelined circuit with a number of stages. In response to the low resolution mode, a number of the stages are bypassed, so that only the needed stages for the smaller number of bits are used. The stages that are bypassed are preferably powered down, but not completely. By maintaining a small amount of bias current to the bypassed stages, they can quickly respond when a switch is made back to full resolution mode.

Abstract translation: 具有低分辨率和高分辨率模式的模数转换器。 响应于低分辨率模式信号，开关电路仅选择某些数字位输出。 在一个实施例中，模数转换器是具有多个级的流水线电路。 响应于低分辨率模式，旁路了多个级，使得仅使用较少位数的所需级。 被绕过的级优选地被断电，但不是完全。 通过保持少量的偏置电流到旁路级，当开关回到全分辨率模式时，它们可以快速响应。

公开(公告)号：US5587684A

公开(公告)日：1996-12-24

申请号：US440272

申请日：1995-05-12

Applicant: Jose A. Salcedo

Inventor： Jose A. Salcedo

IPC: H03K17/22 ,  H03K17/30 ,  G05F1/10

CPC classification number: H03K17/302 ,  H03K17/22

Abstract: A method of including power control features to analog integrated circuits does not require the addition of separate power control input signal pin(s). One or more existing externally applied reference signals are sensed to determine if the signals are within specified operational limits. When the reference signals are outside of the operational limits the internal circuit blocks are switched off to their non-power dissipating state. When the reference signals are within the operational limits the internal circuit blocks are switched on to their normal operating state. This switching can be accomplished in various ways, including but not limited to a single switch in a series with the power supply or many distributed switches in each circuit block or stage.

Abstract translation: 将功率控制特征包括在模拟集成电路中的方法不需要添加单独的功率控制输入信号引脚。 感测一个或多个现有的外部施加的参考信号以确定信号是否在规定的操作限度内。 当参考信号超出操作限制时，内部电路块被切断到其非功耗状态。 当参考信号在操作限制范围内时，内部电路块接通到正常工作状态。 该切换可以以各种方式实现，包括但不限于与电源或每个电路块或级中的许多分布式开关串联的单个开关。