公开(公告)号：US07369766B2

公开(公告)日：2008-05-06

申请号：US10298236

申请日：2002-11-15

申请人： Joseph A. Bannister ,  Joseph D. Touch ,  Purushotham Kamath ,  Aatash Patel ,  John E. McGeehan ,  Alan E. Willner

发明人： Joseph A. Bannister ,  Joseph D. Touch ,  Purushotham Kamath ,  Aatash Patel ,  John E. McGeehan ,  Alan E. Willner

IPC分类号： H04B10/00

CPC分类号： H04Q11/0005 ,  H04Q11/0066 ,  H04Q11/0071 ,  H04Q2011/0039 ,  H04Q2011/0041 ,  H04Q2011/0073

摘要： Systems and techniques to optically boost a router. In general, in one implementation, the technique includes: receiving an optical signal defining a packet of data, initiating electronic routing of the optical packet, and initiating optical routing of the optical packet. The optical routing involves determining forwarding information based on a routing field in the optical packet, and if optical forwarding is available, terminating the electronic routing of the packet before completion of the electronic routing, and forwarding the optical signal, which defines the packet, based on the determined forwarding information.

摘要翻译： 光学提升路由器的系统和技术。 通常，在一个实现中，该技术包括：接收定义数据分组的光信号，启动光分组的电子路由，以及启动光分组的光路由。 光路由涉及基于光分组中的路由字段来确定转发信息，并且如果光转发可用，则在完成电子路由之前终止分组的电子路由，并基于定义分组转发定义分组的光信号 对确定的转发信息。

公开(公告)号：US08306047B2

公开(公告)日：2012-11-06

申请号：US12845616

申请日：2010-07-28

申请人： Joseph D. Touch ,  Joseph Bannister ,  Stephen Suryaputra

发明人： Joseph D. Touch ,  Joseph Bannister ,  Stephen Suryaputra

IPC分类号： H04L12/28

CPC分类号： H04Q11/0005 ,  H04L49/102 ,  H04L49/109 ,  H04Q11/0066 ,  H04Q2011/002 ,  H04Q2011/005

摘要： A packet switch architecture that can switch optical packets at high throughputs without using any random access memory, without fragmenting variable length packets into fixed length fragments and reassembling them, and without converting the optical packets into electronic packets. Programmable delay lines are use which delay the output of each packet for a programmable amount which may be re-programmed while the packet is being delayed by the programmable delay line. Programmable delay line controllers manages the delays imposed by the programmable delay lines so as to have a look-ahead phase during which information about the packets is gathered and a shift phase during which the sequence of packets is shifted to match an output sequence.

摘要翻译： 一种分组交换架构，可以在不使用任何随机存取存储器的情况下以高吞吐量切换光学分组，而不会将可变长度分组分解成固定长度的分段并重新组合，而不将光学分组转换成电子分组。 使用可编程延迟线，其将每个分组的输出延迟可编程量，其可以在分组被可编程延迟线延迟的同时被重新编程。 可编程延迟线控制器​​管理由可编程延迟线施加的延迟，以便具有在其中收集关于分组的信息的前瞻阶段以及分组序列被移位以匹配输出序列的移位阶段。

公开(公告)号：US20110026534A1

公开(公告)日：2011-02-03

申请号：US12845616

申请日：2010-07-28

申请人： Joseph D. Touch ,  Joseph Bannister ,  Stephen Suryaputra

发明人： Joseph D. Touch ,  Joseph Bannister ,  Stephen Suryaputra

IPC分类号： H04L12/56

CPC分类号： H04Q11/0005 ,  H04L49/102 ,  H04L49/109 ,  H04Q11/0066 ,  H04Q2011/002 ,  H04Q2011/005

摘要： A packet switch architecture that can switch optical packets at high throughputs without using any random access memory, without fragmenting variable length packets into fixed length fragments and reassembling them, and without converting the optical packets into electronic packets. Programmable delay lines are use which delay the output of each packet for a programmable amount which may be re-programmed while the packet is being delayed by the programmable delay line. Programmable delay line controllers manages the delays imposed by the programmable delay lines so as to have a look-ahead phase during which information about the packets is gathered and a shift phase during which the sequence of packets is shifted to match an output sequence.

摘要翻译： 一种分组交换架构，可以在不使用任何随机存取存储器的情况下以高吞吐量切换光学分组，而不会将可变长度分组分解成固定长度的分段并重新组合，而不将光学分组转换成电子分组。 使用可编程延迟线，其将每个分组的输出延迟可编程量，其可以在分组被可编程延迟线延迟的同时被重新编程。 可编程延迟线控制器​​管理由可编程延迟线施加的延迟，以便具有在其中收集关于分组的信息的前瞻阶段以及分组序列被移位以匹配输出序列的移位阶段。

公开(公告)号：US07616618B2

公开(公告)日：2009-11-10

申请号：US11289259

申请日：2005-11-29

申请人： P. Vijay Kumar ,  Reza Omrani ,  Joseph D. Touch ,  Alan E. Willner ,  Poorya Saghari

发明人： P. Vijay Kumar ,  Reza Omrani ,  Joseph D. Touch ,  Alan E. Willner ,  Poorya Saghari

IPC分类号： H04B7/216

CPC分类号： H04J14/007 ,  H04J13/004 ,  H04J13/18

摘要： An optical code division multiple access (OCDMA) system includes an optical transmitter system configured to transmit data from a plurality of users through a shared optical channel by encoding the data from each user with a spreading code assigned to that user. Each spreading code includes a unique sequence of T time chips along a time axis. The data from each user is representable by T symbols. The OCDMA system further includes an optical receiver system configured to demodulate the data from each user by correlating signals received from the transmitter system with the spreading code assigned to that user. When transmitting a data symbol for each user, the transmitter system selects one out of T distinct cyclic shifts of the spreading code assigned to that user, and transmits the selected cyclic shift of the assigned spreading code along the time axis.

摘要翻译： 光码分多址（OCDMA）系统包括：光发射机系统，被配置为通过共享光信道从具有分配给该用户的扩展码对来自每个用户的数据进行编码来发送来自多个用户的数据。 每个扩展码包括沿着时间轴的T个时间码片的唯一序列。 来自每个用户的数据可由T符号表示。 OCDMA系统还包括光接收机系统，其被配置为通过将从发射机系统接收的信号与分配给该用户的扩展码相关联来解调来自每个用户的数据。 当为每个用户发送数据符号时，发射机系统选择分配给该用户的扩展码的T个不同循环移位中的一个，并沿着时间轴发送所分配的扩展码的所选循环移位。

公开(公告)号：US5353419A

公开(公告)日：1994-10-04

申请号：US819100

申请日：1992-01-09

申请人： Joseph D. Touch ,  David J. Farber

发明人： Joseph D. Touch ,  David J. Farber

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F9/00 ,  G06F9/30

CPC分类号： G06F9/3814 ,  G06F12/0862 ,  G06F12/0875 ,  G06F9/322 ,  G06F9/3804 ,  G06F9/3808 ,  G06F2212/6028

摘要： A computer architecture which significantly reduces latency in fetching instructions from main memory includes a code-pump located proximate to the memory and a filter cache located proximate to the processor. The code pump reduces latency in fetching instructions by predicting possible instruction streams that may be executed by the processor and passing instructions from all possible streams to the filter cache. The code pump fetches instructions from the memory and partially decodes the instructions to determine their types. Instruction types which may change the flow of the program such as subroutine calls and conditional branches, cause the code pump to concurrently supply instructions from all flow paths that can be predicted from these instructions. To keep track of the possible flow paths, the code pump maintains a data structure which is a combination of multiple stack entries (for call instructions) and tree entries (for branch instructions). The filter cache passes the addresses of fetched instructions back to the code pump. The code pump uses these addresses to determine which flow paths were followed and to deallocate any entries in the data structure which correspond to paths that were not followed.

摘要翻译： 显着减少从主存储器取出指令的延迟的计算机体系结构包括位于存储器附近的代码泵和位于处理器附近的过滤器高速缓存。 代码泵通过预测可能由处理器执行的可能的指令流并且将指令从所有可能的流传递到过滤器高速缓存来减小取指令中的等待时间。 代码泵从存储器中获取指令，并部分解码指令以确定它们的类型。 可能改变程序流程（例如子程序调用和条件分支）的指令类型使代码泵同时从可从这些指令预测的所有流程中提供指令。 为了跟踪可能的流程路径，代码泵维护一个数据结构，它是多个堆栈条目（用于调用指令）和树条目（用于分支指令）的组合。 过滤器缓存将获取的指令的地址传递回代码泵。 代码泵使用这些地址来确定遵循的流程路径，并释放对应于未遵循的路径的数据结构中的任何条目。