公开(公告)号：US09634152B2

公开(公告)日：2017-04-25

申请号：US13537650

申请日：2012-06-29

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Jung Yun Chang

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Jung Yun Chang

IPC分类号： H01L27/088 ,  H01L21/8239 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11582

摘要： A semiconductor device includes memory blocks each configured to comprise a pair of channels, each channel including a pipe channel formed in a pipe gate of the memory block and a drain-side channel and a source-side channel coupled to the pipe channel; first slits placed between the memory blocks adjacent to other memory blocks; and a second slit placed between the source-side channel and the drain-side channel of each pair of channels.

公开(公告)号：US09755085B2

公开(公告)日：2017-09-05

申请号：US13537650

申请日：2012-06-29

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Jung Yun Chang

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Jung Yun Chang

IPC分类号： H01L27/088 ,  H01L21/8239 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11582

CPC分类号： H01L27/11582 ,  H01L21/31111 ,  H01L21/32133 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/1037 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor device includes memory blocks each configured to comprise a pair of channels, each channel including a pipe channel formed in a pipe gate of the memory block and a drain-side channel and a source-side channel coupled to the pipe channel; first slits placed between the memory blocks adjacent to other memory blocks; and a second slit placed between the source-side channel and the drain-side channel of each pair of channels.

公开(公告)号：US20130009229A1

公开(公告)日：2013-01-10

申请号：US13537650

申请日：2012-06-29

申请人： Ki Hong LEE ,  Seung Ho PYI ,  Jung Yun CHANG

发明人： Ki Hong LEE ,  Seung Ho PYI ,  Jung Yun CHANG

IPC分类号： H01L27/088 ,  H01L21/8239

CPC分类号： H01L27/11582 ,  H01L21/31111 ,  H01L21/32133 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/1037 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor device includes memory blocks each configured to comprise a pair of channels, each channel including a pipe channel formed in a pipe gate of the memory block and a drain-side channel and a source-side channel coupled to the pipe channel; first slits placed between the memory blocks adjacent to other memory blocks; and a second slit placed between the source-side channel and the drain-side channel of each pair of channels.

摘要翻译： 半导体器件包括各自被配置为包括一对通道的存储器块，每个通道包括形成在存储器块的管道中的管道通道和与管道通道耦合的漏极侧通道和源极通道; 位于与其他存储块相邻的存储块之间的第一狭缝; 以及设置在每对通道的源极侧通道和漏极侧通道之间的第二狭缝。