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    Charge Cycling By Equalizing the Source and Bit Line Levels Between Pulses During No-Verify Write Operations for NAND Flash Memory
    2.
    发明申请
    Charge Cycling By Equalizing the Source and Bit Line Levels Between Pulses During No-Verify Write Operations for NAND Flash Memory 有权
    通过在NAND闪存的无验证写入操作期间均衡脉冲之间的源和位线电平来进行充电循环

    公开(公告)号：US20130176790A1

    公开(公告)日：2013-07-11

    申请号：US13570826

    申请日：2012-08-09

    申请人： Hao Thai Nguyen ,  Juan Carlos Lee ,  Seungpil Lee ,  Jungmin Park ,  Man Lung Mui

    发明人： Hao Thai Nguyen ,  Juan Carlos Lee ,  Seungpil Lee ,  Jungmin Park ,  Man Lung Mui

    IPC分类号： G11C16/10

    CPC分类号： G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

    摘要： In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. In some cases a non-volatile memory is programmed by an alternating set of pulses, but, for at least some pulses without any intervening verify operations. After a one pulse, but before biasing the memory for the next pulse without an intervening very, the source and bit line levels can be left to float.

    摘要翻译： 在非易失性存储器件中，写入通常由交替的脉冲和验证操作组成。 在脉冲结束时，器件必须被正确偏置才能进行准确的校验，之后器件被重新偏置用于下一个脉冲。 在一些情况下，非易失性存储器通过交替的脉冲组编程，但对于至少一些没有任何中间验证操作的脉冲。 在一个脉冲之后，但是在将存储器偏置在下一个脉冲之前，不会中断，源和位线电平可以保持浮动。