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1.发明公开公开(公告)号：US20240353915A1
公开(公告)日：2024-10-24
申请号：US18763642
申请日：2024-07-03
申请人： Akhilesh S. Thyagaturu , Francesc Guim Bernat , Karthik Kumar , Stephen Thomas Palermo , John J. Browne
发明人： Akhilesh S. Thyagaturu , Francesc Guim Bernat , Karthik Kumar , Stephen Thomas Palermo , John J. Browne
IPC分类号： G06F1/3287
CPC分类号： G06F1/3287
摘要： Systems, apparatus, articles of manufacture, and methods are disclosed to perform dynamic function control. An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to parse a packet for a function directive, activate a function associated with the function directive based on a type of the function directive being associated with an activation instruction, disable the function associated with the function directive based on the type of the function directive being associated with a deactivation instruction, and publish an active function list (AFL) and a passive function list (PFL) based on the type of the function directive.
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公开(公告)号：US20240231924A1
公开(公告)日：2024-07-11
申请号：US18617682
申请日：2024-03-27
申请人： Sharanyan SRIKANTHAN , Karthik KUMAR , Francesc GUIM BERNAT , Rajesh POORNACHANDRAN , Marcos CARRANZA
发明人： Sharanyan SRIKANTHAN , Karthik KUMAR , Francesc GUIM BERNAT , Rajesh POORNACHANDRAN , Marcos CARRANZA
IPC分类号： G06F9/50
CPC分类号： G06F9/5027
摘要： It is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions. The machine-readable instructions comprise instructions to identify a processing flow pattern of a large language model, LLM, wherein the LLM is executed on a processor circuitry comprising a plurality of processor cores and wherein the processing flow pattern comprising a plurality of processing phases. The machine-readable instructions further comprise instructions to identify a processing phase of the LLM from the processing flow pattern. The machine-readable instructions further comprise instructions to allocate processing resources to the processor circuitry based on the identified processing phase of the LLM.
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公开(公告)号：US20240126579A1
公开(公告)日：2024-04-18
申请号：US18397256
申请日：2023-12-27
申请人： Akhilesh Thyagaturu , Jonathan L. Kyle , Mohit Kumar Garg , Karthik Kumar , Francesc Guim Bernat
发明人： Akhilesh Thyagaturu , Jonathan L. Kyle , Mohit Kumar Garg , Karthik Kumar , Francesc Guim Bernat
IPC分类号： G06F9/455
CPC分类号： G06F9/45541 , G06F9/45558 , G06F2009/45595
摘要： A server platform in a cloud computing system is determined to be in an unused state and a request from a remote computing system outside the data center system is received to control hardware of at least one of the server platforms of the cloud computing systems. A bare-metal-as-is (BMAI) session is initiated for the remote computing system to use the server platform based on the unused state, wherein exclusive control of at least a portion of hardware of the server platform is temporarily handed over to the remote computing system in the BMAI session. Control of the portion of the hardware of the server platform is reclaimed based on an end of the BMAI session.
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公开(公告)号：US20230342223A1
公开(公告)日：2023-10-26
申请号：US18216790
申请日：2023-06-30
IPC分类号： G06F9/50
CPC分类号： G06F9/5088 , G06F9/5072 , H04L67/10
摘要： Various aspects of methods, systems, and use cases include edge resource management, such as of a processor of an edge device. The edge device may include a processor to execute an application and a device including an interface to the processor and a network interface. The device may include circuitry to monitor a status of the processor; and based on the status and the application having an associated requirement, initiate a migration of execution of the application from the processor.
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公开(公告)号：US20230240055A1
公开(公告)日：2023-07-27
申请号：US18194522
申请日：2023-03-31
IPC分类号： H05K7/20
CPC分类号： H05K7/20836 , H05K7/20172 , H05K7/20209
摘要： Methods and apparatus to manage noise in computing systems are disclosed. An example server includes a housing to at least partially contain components of the server, a transducer to output an indication of noise detected outside of the housing, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to adjust the operation of the server based on the output of the transducer to reduce noise.
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公开(公告)号：US20230135645A1
公开(公告)日：2023-05-04
申请号：US18090764
申请日：2022-12-29
IPC分类号： G06F9/50
摘要： Various approaches for deploying and controlling distributed compute operations with the use of infrastructure processing units (IPUs) and similar networked processing units are disclosed. A system that includes a networked processing unit may perform workload processing with operations that: receive, from another networked processing unit, workload information for a workload, for a workload having respective tasks to be processed among distributed computing entities; perform an analysis of network conditions for a predicted execution of the workload, based on the workload information, to analyze network availability among the distributed computing entities; perform an analysis of compute conditions for the predicted execution of the workload, based on the workload information, to analyze processing availability among the distributed computing entities; and identify locations of the distributed computing entities to deploy the workload, based on the analysis of network conditions and the analysis of compute conditions.
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公开(公告)号：US20220012088A1
公开(公告)日：2022-01-13
申请号：US17485279
申请日：2021-09-24
摘要： Techniques for expanded trusted domains are disclosed. In the illustrative embodiment, a trusted domain can be established that includes hardware components from a processor as well as an off-load device. The off-load device may provide compute resources for the trusted domain. The trusted domain can be expanded and contracted on-demand, allowing for a flexible approach to creating and using trusted domains.
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公开(公告)号：US20210064531A1
公开(公告)日：2021-03-04
申请号：US17092803
申请日：2020-11-09
IPC分类号： G06F12/0817
摘要： Methods and apparatus for software-defined coherent caching of pooled memory. The pooled memory is implemented in an environment having a disaggregated architecture where compute resources such as compute platforms are connected to disaggregated memory via a network or fabric. Software-defined caching policies are implemented in hardware in a processor SoC or discrete device such as a Network Interface Controller (NIC) by programming logic in an FPGA or accelerator on the SoC or discrete device. The programmed logic is configured to implement software-defined caching policies in hardware for effecting disaggregated memory (DM) caching in an associated DM cache of at least a portion of an address space allocated for the software application in the disaggregated memory. In connection with DM cache operations, such as cache lines evicted from a CPU, logic implemented in hardware determines whether a cache line in a DM cache is to be convicted and implements the software-defined caching policy for the DM cache including associated memory coherency operations.
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公开(公告)号：US20200026575A1
公开(公告)日：2020-01-23
申请号：US16586576
申请日：2019-09-27
IPC分类号： G06F9/50
摘要： Methods, apparatus, systems and machine-readable storage media of an edge computing device which is enabled to access and select the use of local or remote acceleration resources for edge computing processing is disclosed. In an example, an edge computing device obtains first telemetry information that indicates availability of local acceleration circuitry to execute a function, and obtains second telemetry that indicates availability of a remote acceleration function to execute the function. An estimated time (and cost or other identifiable or estimateable considerations) to execute the function at the respective location is identified. The use of the local acceleration circuitry or the remote acceleration resource is selected based on the estimated time and other appropriate factors in relation to a service level agreement.
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公开(公告)号：US20190041960A1
公开(公告)日：2019-02-07
申请号：US16011842
申请日：2018-06-19
申请人： Francesc Guim Bernat , Suraj Prabhakaran , Timothy Verrall , Karthik Kumar , Mark A. Schmisseur
发明人： Francesc Guim Bernat , Suraj Prabhakaran , Timothy Verrall , Karthik Kumar , Mark A. Schmisseur
摘要： In one embodiment, an apparatus of an edge computing system includes memory that includes instructions and processing circuitry coupled to the memory. The processing circuitry implements the instructions to process a request to execute at least a portion of a workflow on pooled computing resources, the workflow being associated with a particular tenant, determine an amount of power to be allocated to particular resources of the pooled computing resources for execution of the portion of the workflow based on a power budget associated with the tenant and a current power cost, and control allocation of the determined amount of power to the particular resources of the pooled computing resources during execution of the portion of the workflow.
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