公开(公告)号：US07406544B2

公开(公告)日：2008-07-29

申请号：US11029509

申请日：2005-01-06

申请人： Kazumasa Ozawa

发明人： Kazumasa Ozawa

IPC分类号： G06F3/00

CPC分类号： G06F13/4027 ,  Y02D10/14 ,  Y02D10/151

摘要： A semiconductor integrated circuit includes a bridge circuit which controls a data transfer of a bus line, peripheral circuits which are connected to the bridge circuit through the busline, and a control circuit which is formed at the peripheral circuits. The control circuit receives a select signal and controls the data transfer in the peripheral circuits in accordance with a logic state of the select signal.

公开(公告)号：US20050125587A1

公开(公告)日：2005-06-09

申请号：US11029485

申请日：2005-01-06

申请人： Kazumasa Ozawa

发明人： Kazumasa Ozawa

IPC分类号： G06F13/14 ,  G06F3/00 ,  G06F13/00 ,  G06F13/36 ,  G06F13/40 ,  H01L21/822 ,  H01L27/04

CPC分类号： G06F13/4027 ,  Y02D10/14 ,  Y02D10/151

摘要： A semiconductor integrated circuit includes a bridge circuit which controls a data transfer of a bus line, peripheral circuits which are connected to the bridge circuit through the busline, and a control circuit which is formed at the peripheral circuits. The control circuit receives a select signal and controls the data transfer in the peripheral circuits in accordance with a logic state of the select signal.

摘要翻译： 半导体集成电路包括控制总线的数据传送的桥接电路，通过总线连接到桥式电路的外围电路以及形成在外围电路上的控制电路。 控制电路根据选择信号的逻辑状态接收选择信号并控制外围电路中的数据传送。

公开(公告)号：US5926588A

公开(公告)日：1999-07-20

申请号：US507378

申请日：1995-08-21

申请人： Takashi Murakami ,  Tsutomu Watanabe ,  Kazumasa Ozawa ,  Hisao Maki ,  Kazuhito Saito ,  Nobuo Tomita

发明人： Takashi Murakami ,  Tsutomu Watanabe ,  Kazumasa Ozawa ,  Hisao Maki ,  Kazuhito Saito ,  Nobuo Tomita

IPC分类号： G02B6/35 ,  G02B6/26

CPC分类号： G02B6/3506 ,  G02B6/3548 ,  G02B6/3568 ,  G02B6/358 ,  G02B6/3582

摘要： An optical switch of the present invention comprises an optical fiber arranging member in which tip ends of a plurality of first optical fibers are juxtaposed, a movable arm facing the optical fiber arranging member and fixing a tip end of a second optical fiber, and a drive mechanism For driving at least one of the optical fiber arranging member and the movable arm, for switching of optical connection, in an arrangement direction of the first optical fibers and in a direction perpendicular to the arrangement direction of the first optical fibers to optically couple the second optical fiber with the first optical fiber, wherein the optical fiber arranging member and the movable arm are encased in a sealing case and wherein an antireflection agent is filled in the sealing case.

摘要翻译： PCT No.PCT / JP94 / 02150 Sec。 371日期1995年8月21日 102（e）日期1995年8月21日PCT 1994年12月20日PCT公布。 公开号WO95 / 17697 1994年12月20日本发明的光开关包括：多个第一光纤的末端并置的光纤布置构件;面对光纤布置构件的可动臂，并固定第二光纤的末端 光纤和驱动机构为了驱动光纤排列构件和可动臂中的至少一个，用于切换光学连接，在第一光纤的布置方向上并且在垂直于第一光纤的布置方向的方向上 将所述第二光纤与所述第一光纤光学耦合的光纤，其中所述光纤排列构件和所述可动臂被封装在密封壳体中，并且其中所述防反射剂填充在所述密封壳体中。

公开(公告)号：US08909995B2

公开(公告)日：2014-12-09

申请号：US11197403

申请日：2005-08-05

申请人： Kazumasa Ozawa

发明人： Kazumasa Ozawa

IPC分类号： G06F11/00 ,  G06F11/07

CPC分类号： G06F11/0757

摘要： A microcomputer or microcontroller with a watchdog timer-counter also has an external reset signal generator. When the central processing unit of the microcomputer or microcontroller fails to execute its control program correctly, the watchdog timer-counter generates an internal reset signal for a first interval, resetting the central processing unit, and the external reset signal generator generates an external reset signal for a second interval, different from the first interval. The length of the second interval can be set to match the requirements of external peripheral devices to which the external reset signal is supplied.

摘要翻译： 具有看门狗定时器计数器的微计算机或微控制器还具有外部复位信号发生器。 当微计算机或微控制器的中央处理单元无法正确执行其控制程序时，看门狗定时器计数器产生第一间隔的内部复位信号，复位中央处理单元，外部复位信号发生器产生外部复位信号 与第一个间隔不同的第二个间隔。 可以将第二间隔的长度设置为与外部复位信号所提供的外部设备的要求相匹配。

公开(公告)号：US07882376B2

公开(公告)日：2011-02-01

申请号：US11782006

申请日：2007-07-24

申请人： Kazumasa Ozawa

发明人： Kazumasa Ozawa

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  B23K11/24

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

摘要： The present invention provides an LSI which comprises first circuit areas (e.g., an I/O area and a VBAT area) in which power is always held ON, a second circuit area (e.g., a CORE area) capable of ON/OFF-switching of the power, a power control circuit which is provided within the corresponding first circuit area and outputs a control signal for performing power control on the second circuit area, and a reset signal detection circuit which is provided within the corresponding first circuit area and detects an internal standby reset signal or an external standby reset signal to control the operation of the power control circuit.

摘要翻译： 本发明提供了一种LSI，其包括电源始终保持接通的第一电路区域（例如，I / O区域和VBAT区域），能够进行ON / OFF切换的第二电路区域（例如，CORE区域） 功率控制电路，其设置在相应的第一电路区域内，并输出用于对第二电路区域进行功率控制的控制信号;以及复位信号检测电路，其设置在相应的第一电路区域内，并检测 内部待机复位信号或外部待机复位信号来控制电源控制电路的工作。

公开(公告)号：US07333151B2

公开(公告)日：2008-02-19

申请号：US11049327

申请日：2005-02-03

申请人： Kazumasa Ozawa

发明人： Kazumasa Ozawa

IPC分类号： H04N5/06

CPC分类号： G09G5/008 ,  H04N5/06 ,  H04N5/073 ,  H04N9/44

摘要： A circuit which generates a dot clock synchronized to an external video signal which can ensure a pulse width allowed by a device which is supplied with the dot clock. A high frequency clock is divided to generate a first dot clock, and the phase is initialized in accordance with information on a previously set frequency division ratio upon detection of a significant edge of a horizontal synchronization signal. Also, a second dot clock, the logical level of which changes every minimum allowable period, is formed from the high frequency clock in accordance with information on a previously set minimum allowable period, and the phase is modified upon detection of the significant edge such that the minimum allowable period is ensured for the logical level period even before and after the detection. The second dot clock is selected upon detection of the significant edge, and afterwards, the first dot clock is selected when a confirmation can be made that the timing of the first dot clock is coincident with or behind the timing of the second dot clock.

摘要翻译： 产生与外部视频信号同步的点时钟的电路，该外部视频信号可以确保提供有点时钟的装置允许的脉冲宽度。 高频时钟被分割以产生第一点时钟，并且在检测到水平同步信号的有效边沿时，根据关于先前设置的分频比的信息来初始化相位。 此外，根据关于先前设定的最小允许周期的信息，从高频时钟形成其逻辑电平在每个最小允许周期改变的第二点时钟，并且在检测到有效边沿时修改相位，使得 即使在检测之前和之后，逻辑电平周期也能确保最小允许周期。 在检测到有效边缘时选择第二点时钟，然后当可以确认第一点时钟的定时与第二点时钟的定时一致或更迟时，选择第一点时钟。

公开(公告)号：US07181549B2

公开(公告)日：2007-02-20

申请号：US10173677

申请日：2002-06-19

申请人： Kazumasa Ozawa

发明人： Kazumasa Ozawa

IPC分类号： G06F3/00

CPC分类号： G06F13/4027 ,  Y02D10/14 ,  Y02D10/151

摘要： A semiconductor integrated circuit includes a bridge circuit which controls a data transfer of a bus line, peripheral circuits which are connected to the bridge circuit through the busline, and a control circuit which is formed at the peripheral circuits. The control circuit receives a select signal and controls the data transfer in the peripheral circuits in accordance with a logic state of the select signal.

摘要翻译： 半导体集成电路包括控制总线的数据传送的桥接电路，通过总线连接到桥式电路的外围电路以及形成在外围电路上的控制电路。 控制电路根据选择信号的逻辑状态接收选择信号并控制外围电路中的数据传送。

公开(公告)号：US20060053349A1

公开(公告)日：2006-03-09

申请号：US11197403

申请日：2005-08-05

申请人： Kazumasa Ozawa

发明人： Kazumasa Ozawa

IPC分类号： G06F11/00

CPC分类号： G06F11/0757

摘要： A microcomputer or microcontroller with a watchdog timer-counter also has an external reset signal generator. When the central processing unit of the microcomputer or microcontroller fails to execute its control program correctly, the watchdog timer-counter generates an internal reset signal for a first interval, resetting the central processing unit, and the external reset signal generator generates an external reset signal for a second interval, different from the first interval. The length of the second interval can be set to match the requirements of external peripheral devices to which the external reset signal is supplied.

摘要翻译： 具有看门狗定时器计数器的微计算机或微控制器还具有外部复位信号发生器。 当微计算机或微控制器的中央处理单元无法正确执行其控制程序时，看门狗定时器计数器产生第一间隔的内部复位信号，复位中央处理单元，外部复位信号发生器产生外部复位信号 与第一个间隔不同的第二个间隔。 可以将第二间隔的长度设置为与外部复位信号所提供的外部设备的要求相匹配。

公开(公告)号：US20050125588A1

公开(公告)日：2005-06-09

申请号：US11029486

申请日：2005-01-06

申请人： Kazumasa Ozawa

发明人： Kazumasa Ozawa

IPC分类号： G06F13/14 ,  G06F3/00 ,  G06F13/00 ,  G06F13/36 ,  G06F13/40 ,  H01L21/822 ,  H01L27/04

CPC分类号： G06F13/4027 ,  Y02D10/14 ,  Y02D10/151

摘要： A semiconductor integrated circuit includes a bridge circuit which controls a data transfer of a bus line, peripheral circuits which are connected to the bridge circuit through the bus line, and a control circuit which is formed at the peripheral circuits. The control circuit receives a select signal and controls the data transfer in the peripheral circuits in accordance with a logic state of the select signal.

摘要翻译： 半导体集成电路包括控制总线线路的数据传输的桥接电路，通过总线连接到桥接电路的外围电路以及形成在外围电路上的控制电路。 控制电路根据选择信号的逻辑状态接收选择信号并控制外围电路中的数据传送。

公开(公告)号：US20050120156A1

公开(公告)日：2005-06-02

申请号：US11029509

申请日：2005-01-06

申请人： Kazumasa Ozawa

发明人： Kazumasa Ozawa

IPC分类号： G06F13/14 ,  G06F3/00 ,  G06F13/00 ,  G06F13/36 ,  G06F13/40 ,  H01L21/822 ,  H01L27/04

CPC分类号： G06F13/4027 ,  Y02D10/14 ,  Y02D10/151

摘要： A semiconductor integrated circuit includes a bridge circuit which controls a data transfer of a bus line, peripheral circuits which are connected to the bridge circuit through the busline, and a control circuit which is formed at the peripheral circuits. The control circuit receives a select signal and controls the data transfer in the peripheral circuits in accordance with a logic state of the select signal.