公开(公告)号：US20120212475A1

公开(公告)日：2012-08-23

申请号：US13462296

申请日：2012-05-02

申请人： Kenichi TAJIKA ,  Hiroshi SHIROUZU

发明人： Kenichi TAJIKA ,  Hiroshi SHIROUZU

IPC分类号： G06F3/038

CPC分类号： G09G3/3233 ,  G09G3/006 ,  G09G3/3283 ,  G09G2330/12

摘要： An inspection method for an active-matrix substrate including the scanning lines, the data lines, the pixels disposed in matrix, and the power lines. The pixel includes: an organic EL device; a drive transistor; a capacitor; a selection transistor having a gate connected to the scanning line and connected between the data line and the gate of the drive transistor, and the guard potential transistor having a gate connected to a source of the selection transistor, a source connected to a drain of the selection transistor, and a drain connected to the power line. The inspection method includes: a writing process for writing a charge in the capacitor; a reading process for reading the written charged from the capacitor; and a holding process for holding the charge for a predetermined period from the end of the writing process to the start of the reading process.

摘要翻译： 包括扫描线，数据线，矩阵排列的像素和电源线的有源矩阵基板的检查方法。 像素包括：有机EL器件; 驱动晶体管; 电容器 选择晶体管，其栅极连接到扫描线并且连接在数据线和驱动晶体管的栅极之间，并且保护电位晶体管具有连接到选择晶体管的源极的栅极，源极连接到选择晶体管的漏极 选择晶体管和连接到电力线的漏极。 检查方法包括：写入电容器中的电荷的写入过程; 读取从电容器写入的读取过程; 以及保持处理，用于将写入处理结束之后的预定时间的费用保持到开始读取处理。

公开(公告)号：US20070007642A1

公开(公告)日：2007-01-11

申请号：US11475184

申请日：2006-06-27

申请人： Kenichi Tajika

发明人： Kenichi Tajika

IPC分类号： H01L23/52

CPC分类号： H01L23/5286 ,  H01L25/18 ,  H01L2924/0002 ,  H03K19/0016 ,  H01L2924/00

摘要： A semiconductor integrated circuit device includes a functional circuit block, a power supply for supplying power to the functional circuit block, a power supply interruption circuit disposed between the functional circuit block and the power supply and including a plurality of switching elements, and a power supply interruption control circuit for individually driving the switching elements. The functional circuit block is formed by integrating functional circuits, such as a logic circuit and a memory circuit. The functional circuits are formed with power supply terminals, respectively, and the power supply terminals are electrically connected through power supply interconnects to the switching elements. The power supply interconnects have the same length.

摘要翻译： 一种半导体集成电路装置，包括功能电路块，向功能电路块供电的电源，设置在功能电路块与电源之间的电源中断电路，包括多个开关元件，电源 用于单独驱动开关元件的中断控制电路。 功能电路块通过集成诸如逻辑电路和存储电路的功能电路而形成。 功能电路分别由电源端子形成，电源端子通过电源互连电连接到开关元件。 电源互连具有相同的长度。

公开(公告)号：US08537151B2

公开(公告)日：2013-09-17

申请号：US13462296

申请日：2012-05-02

申请人： Kenichi Tajika ,  Hiroshi Shirouzu

发明人： Kenichi Tajika ,  Hiroshi Shirouzu

IPC分类号： G06F3/038 ,  G09G5/00 ,  G09G3/30 ,  G09G3/10 ,  G02F1/1333

CPC分类号： G09G3/3233 ,  G09G3/006 ,  G09G3/3283 ,  G09G2330/12

摘要： An inspection method for an active-matrix substrate including the scanning lines, the data lines, the pixels disposed in matrix, and the power lines. The pixel includes: an organic EL device; a drive transistor; a capacitor; a selection transistor having a gate connected to the scanning line and connected between the data line and the gate of the drive transistor, and the guard potential transistor having a gate connected to a source of the selection transistor, a source connected to a drain of the selection transistor, and a drain connected to the power line. The inspection method includes: a writing process for writing a charge in the capacitor; a reading process for reading the written charged from the capacitor; and a holding process for holding the charge for a predetermined period from the end of the writing process to the start of the reading process.

摘要翻译： 包括扫描线，数据线，矩阵排列的像素和电源线的有源矩阵基板的检查方法。 像素包括：有机EL器件; 驱动晶体管; 电容器 选择晶体管，其栅极连接到扫描线并且连接在数据线和驱动晶体管的栅极之间，并且保护电位晶体管具有连接到选择晶体管的源极的栅极，源极连接到选择晶体管的漏极 选择晶体管和连接到电力线的漏极。 检查方法包括：写入电容器中的电荷的写入过程; 读取从电容器写入的读取过程; 以及保持处理，用于将写入处理结束之后的预定时间的费用保持到开始读取处理。

公开(公告)号：US20120326744A1

公开(公告)日：2012-12-27

申请号：US13602881

申请日：2012-09-04

申请人： Kenichi TAJIKA ,  Hiroshi SHIROUZU

发明人： Kenichi TAJIKA ,  Hiroshi SHIROUZU

IPC分类号： G01R31/26 ,  H01L33/08 ,  H01L27/15

CPC分类号： G09G3/006 ,  G01R31/26 ,  G09G3/3225 ,  G09G3/3648 ,  G09G2330/10 ,  G09G2330/12 ,  H01L27/3262 ,  H01L27/3276

摘要： An active-matrix substrate includes: a substrate; gate lines disposed on the substrate; source lines disposed on the substrate in a direction that crosses the gate lines; a first terminal provided for each of data line blocks obtained by grouping every m-lines (m being an integer greater than or equal to 2) of the source lines into a block; a first selection circuit provided for each of the data line blocks, for causing conduction between the first terminal and at least one source line selected from among the m source lines; a second terminal provided for every n-blocks (n being an integer greater than or equal to 2) of the data line blocks; and a second selection terminal provided for every n-blocks of the data line blocks, for causing conduction between the second terminal and at least one source line selected from among the m×n source lines.

摘要翻译： 有源矩阵基板包括：基板; 设置在基板上的栅极线; 源极线设置在与栅极线交叉的方向上的衬底上; 通过将源极线的每m行（m为大于或等于2的整数）分组为块而获得的每个数据线块提供的第一端子; 为每个所述数据线块设置的第一选择电路，用于使所述第一端子与从所述m条源极线中选择的至少一条源极线之间导通; 为数据线块的每个n个块（n为大于或等于2的整数）提供的第二终端; 以及为每个n个数据线块设置的第二选择端子，用于使第二端子与从m×n条源极线中选择的至少一条源极线之间导通。

公开(公告)号：US07181709B2

公开(公告)日：2007-02-20

申请号：US10766954

申请日：2004-01-30

申请人： Kenichi Tajika ,  Hiroki Tomoshige ,  Minoru Itoh

发明人： Kenichi Tajika ,  Hiroki Tomoshige ,  Minoru Itoh

IPC分类号： G06F17/50

CPC分类号： G06F1/10

摘要： In a clock delay adjusting method of a semiconductor integrated circuit device, a plurality of source points for adjusting a clock delay is provided to synchronize a value of the clock delay from each of the source points of each of hierarchical blocks in a semiconductor chip to a clock input circuit operating synchronously with a clock, according to circuit design conditions of the hierarchical blocks. Area terminals are provided in the source points, respectively. A clock input terminal of the semiconductor chip and each area terminal are connected through a clock line so as to be clock distributed over a hierarchical top. A clock delay between the hierarchical blocks is adjusted.

摘要翻译： 在半导体集成电路装置的时钟延迟调整方法中，提供用于调整时钟延迟的多个源极点，以使来自半导体芯片中的每个分级块的每个源点的时钟延迟的值同步到 时钟输入电路与时钟同步工作，根据电路设计条件分层。 分别在源点提供区域终端。 半导体芯片和每个区域终端的时钟输入端子通过时钟线连接，以便在分级顶部上分布时钟。 调整分层块之间的时钟延迟。

公开(公告)号：US09293074B2

公开(公告)日：2016-03-22

申请号：US13602881

申请日：2012-09-04

申请人： Kenichi Tajika ,  Hiroshi Shirouzu

发明人： Kenichi Tajika ,  Hiroshi Shirouzu

IPC分类号： G01R31/02 ,  G01R31/26 ,  G09G3/00 ,  H01L27/32 ,  G09G3/32 ,  G09G3/36

CPC分类号： G09G3/006 ,  G01R31/26 ,  G09G3/3225 ,  G09G3/3648 ,  G09G2330/10 ,  G09G2330/12 ,  H01L27/3262 ,  H01L27/3276

摘要： An active-matrix substrate includes: a substrate; gate lines disposed on the substrate; source lines disposed on the substrate in a direction that crosses the gate lines; a first terminal provided for each of data line blocks obtained by grouping every m-lines (m being an integer greater than or equal to 2) of the source lines into a block; a first selection circuit provided for each of the data line blocks, for causing conduction between the first terminal and at least one source line selected from among the m source lines; a second terminal provided for every n-blocks (n being an integer greater than or equal to 2) of the data line blocks; and a second selection terminal provided for every n-blocks of the data line blocks, for causing conduction between the second terminal and at least one source line selected from among the m×n source lines.

摘要翻译： 有源矩阵基板包括：基板; 设置在基板上的栅极线; 源极线设置在与栅极线交叉的方向上的衬底上; 通过将源极线的每m行（m为大于或等于2的整数）分组为块而获得的每个数据线块提供的第一端子; 为每个所述数据线块设置的第一选择电路，用于使所述第一端子与从所述m条源极线中选择的至少一条源极线之间导通; 为数据线块的每个n个块（n为大于或等于2的整数）提供的第二终端; 以及为每个n个数据线块设置的第二选择端子，用于使第二端子与从m×n条源极线中选择的至少一条源极线之间导通。

公开(公告)号：US08421200B2

公开(公告)日：2013-04-16

申请号：US11730635

申请日：2007-04-03

申请人： Kenichi Tajika ,  Takehisa Kishimoto

发明人： Kenichi Tajika ,  Takehisa Kishimoto

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/552 ,  H01L25/50 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device is made by stacking a plurality of semiconductor chips. The semiconductor integrated circuit device includes: a penetrating electrode formed to penetrate the plurality of semiconductor chips; a plurality of electrodes formed in respective layers constituting each of the plurality of semiconductor chips and having respective openings within which the penetrating electrode penetrates; and a plurality of vias each of which electrically connects electrodes of the plurality of electrodes located in adjacent layers. The vias are each formed so that the side face thereof is in contact with the penetrating electrode.

摘要翻译： 通过堆叠多个半导体芯片来制造半导体集成电路器件。 半导体集成电路器件包括：形成为穿透多个半导体芯片的穿透电极; 多个电极，形成在构成所述多个半导体芯片中的每一个的各个层中，并且具有穿透电极穿透的各自的开口; 以及多个通孔，每个通孔电连接位于相邻层中的多个电极的电极。 通孔各自形成为使得其侧面与穿透电极接触。

公开(公告)号：US20120326176A1

公开(公告)日：2012-12-27

申请号：US13472991

申请日：2012-05-16

申请人： Hiroshi SHIROUZU ,  Kenichi TAJIKA

发明人： Hiroshi SHIROUZU ,  Kenichi TAJIKA

IPC分类号： H01L33/62 ,  H01L21/66

CPC分类号： H01L27/3265 ,  H01L27/1255 ,  H01L2924/0002 ,  H01L2924/00

摘要： A capacitor unit in a display device includes: a capacitor element having a first capacitor electrode connected to a power line and provided in a GM electrode layer and a second capacitor electrode connected to a line and provided in an SD electrode layer; a backup capacitor element having a first backup capacitor electrode provided in the GM electrode layer and a second backup capacitor electrode connected to the power line and provided in the SD electrode layer; a disconnect-able portion at which a connection between the second capacitor electrode and the line can be disconnected; and a connectable portion at which the first backup capacitor electrode and the line can be connected, and the disconnect-able portion and the connectable portion are arranged at a position in which the disconnect-able portion and the connectable portion overlap in a stacking direction.

摘要翻译： 显示装置中的电容器单元包括：具有连接到电力线并且设置在GM电极层中的第一电容器电极和连接到线并且设置在SD电极层中的第二电容器电极的电容器元件; 备有电容器元件，其具有设置在所述GM电极层中的第一备用电容器电极和连接到所述电力线并设置在所述SD电极层中的第二备用电容器电极; 可断开第二电容器电极和线路之间的连接的断开部分; 以及可连接第一备用电容器电极和线路的可连接部分，并且可断开部分和可连接部分布置在可断开部分和可连接部分在堆叠方向上重叠的位置。

公开(公告)号：US20120056538A1

公开(公告)日：2012-03-08

申请号：US13295471

申请日：2011-11-14

申请人： Hiroshi SHIROUZU ,  Kenichi TAJIKA

发明人： Hiroshi SHIROUZU ,  Kenichi TAJIKA

IPC分类号： H01J7/44 ,  H05K13/00

CPC分类号： H01L27/3265 ,  H01L27/1255 ,  H01L2251/568 ,  Y10T29/49002

摘要： The display device includes stacked layers including a display element layer and a control layer including a capacitor including an upper electrode layer and a lower electrode layer that face each other in a layer-stacking direction, wherein the upper electrode layer includes a first upper capacitor electrode connecting two circuit elements, a disconnectable portion, and a second upper capacitor electrode connected to the first upper electrode layer through the disconnectable portion, and the lower electrode layer includes a first lower capacitor electrode connecting two circuit elements, a disconnectable portion, and a second lower capacitor electrode connected to the first lower electrode layer through the disconnectable portion. The capacitor has a capacitance each between the first upper capacitor electrode and the second lower capacitor electrode, and the first lower capacitor electrode and the second upper capacitor electrode.

摘要翻译： 显示装置包括层叠层，其包括显示元件层和包括电容器的控制层，该电容器包括层叠方向彼此相对的上电极层和下电极层，其中，上电极层包括第一上电容器电极 连接两个电路元件，可断开部分和通过可断开部分连接到第一上电极层的第二上电容器电极，下电极层包括连接两个电路元件的第一下电容器电极，可断开部分和第二 通过可断开部分连接到第一下电极层的下电容器电极。 电容器在第一上电容电极电极和第二下电容电极之间具有电容，第一下电容电极和第二上电容器电极。

公开(公告)号：US07626266B2

公开(公告)日：2009-12-01

申请号：US11475184

申请日：2006-06-27

申请人： Kenichi Tajika

发明人： Kenichi Tajika

IPC分类号： H01L23/52 ,  H01L23/02 ,  H03K5/15

CPC分类号： H01L23/5286 ,  H01L25/18 ,  H01L2924/0002 ,  H03K19/0016 ,  H01L2924/00

摘要： A semiconductor integrated circuit device includes a functional circuit block, a power supply for supplying power to the functional circuit block, a power supply interruption circuit disposed between the functional circuit block and the power supply and including a plurality of switching elements, and a power supply interruption control circuit for individually driving the switching elements. The functional circuit block is formed by integrating functional circuits, such as a logic circuit and a memory circuit. The functional circuits are formed with power supply terminals, respectively, and the power supply terminals are electrically connected through power supply interconnects to the switching elements. The power supply interconnects have the same length.

摘要翻译： 一种半导体集成电路装置，包括功能电路块，向功能电路块供电的电源，设置在功能电路块与电源之间的电源中断电路，包括多个开关元件，电源 用于单独驱动开关元件的中断控制电路。 功能电路块通过集成诸如逻辑电路和存储电路的功能电路而形成。 功能电路分别由电源端子形成，电源端子通过电源互连电连接到开关元件。 电源互连具有相同的长度。