公开(公告)号：US08387113B2

公开(公告)日：2013-02-26

申请号：US12298774

申请日：2007-05-10

申请人： Hidetoshi Shimada ,  Norio Fujimori ,  Keiichi Komaki ,  Keisuke Koide ,  Tsuyoshi Ookubo ,  Kenichiro Kamijo ,  Daiki Yokoyama ,  Kenichi Takahira ,  Katsuhisa Tatsukawa

发明人： Hidetoshi Shimada ,  Norio Fujimori ,  Keiichi Komaki ,  Keisuke Koide ,  Tsuyoshi Ookubo ,  Kenichiro Kamijo ,  Daiki Yokoyama ,  Kenichi Takahira ,  Katsuhisa Tatsukawa

IPC分类号： G06F7/04

CPC分类号： G06F21/71 ,  G06F1/28 ,  G06F21/40 ,  G06F21/42 ,  G06F21/44 ,  G06F21/81 ,  G06F21/85 ,  G06F2221/2103 ,  G06F2221/2129 ,  G06F2221/2153

摘要： An authenticating system according to the present invention has a characteristic structure of which an authenticating section 32 of a note type PC 10 and an authenticating section 42 of a battery 20 are directly connected through I/O ports 51 and 61, respectively. Thus, the authenticating system according to the present invention can be relatively easily accomplished using a conventional system. The present invention can be applied to a system that is composed of a plurality of electronic devices that perform an authenticating process.

摘要翻译： 根据本发明的认证系统具有以下特征结构：便携式PC10的认证部分32和电池20的认证部分42分别通过I / O端口51和61直接连接。 因此，根据本发明的认证系统可以使用常规系统相对容易地实现。 本发明可以应用于由执行认证处理的多个电子设备组成的系统。

公开(公告)号：US5671254A

公开(公告)日：1997-09-23

申请号：US449546

申请日：1995-05-24

申请人： Yoshishige Nagata ,  Kenichi Takahira

发明人： Yoshishige Nagata ,  Kenichi Takahira

IPC分类号： H02J7/00 ,  G06K7/00 ,  G06K7/10 ,  H02J50/00 ,  H02J50/10 ,  H04B1/40 ,  H04B1/59 ,  H04B7/26 ,  H04L27/18 ,  H04L27/20 ,  H04L27/22 ,  H04L27/233 ,  H04W52/00 ,  H04W56/00 ,  H04W84/10 ,  H04L27/14 ,  H04L27/16

CPC分类号： H04L27/2332 ,  G06K7/0008 ,  H04L27/18

摘要： A modulator used in an IC card reader/writer includes a phase variation detector for detecting a varying point of the phase of a modulated signal, a signal processing circuit for modifying the modulated signal for a half period at the phase varying point to have a frequency and amplitude twice those of the modulated signal, a first Miller integrator for integrating the modified signal to produce a triangular wave signal, and a second Miller integrator for integrating the triangular wave signal to produce a sinusoidal wave signal having a continuous phase. A demodulator used in the reader/writer includes a sync control circuit which controls a carrier sync signal generation circuit thereby to control the phase of a carrier sync signal in response to the discrimination as to whether the carrier sync signal is in lead-phase or lag-phase relative to the signal modulated based on binary phase shift keying (BPSK). A control data signal and non-modulated carrier wave sent from the reader/writer to the IC card are converted into power for use by the IC card.

摘要翻译： 在IC卡读写器中使用的调制器包括用于检测调制信号的相位的变化点的相位变化检测器，用于在相位变化点修正半个周期的调制信号的信号处理电路，以具有频率 振幅是调制信号的两倍，第一米勒积分器，用于积分修正信号以产生三角波信号，第二米勒积分器用于积分三角波信号以产生具有连续相位的正弦波信号。 在读/写器中使用的解调器包括同步控制电路，其控制载波同步信号产生电路，从而响应于载波同步信号是否处于超前或滞后的判别来控制载波同步信号的相位 相位相对于基于二进制相移键控（BPSK）调制的信号。 将从读写器发送到IC卡的控制数据信号和未调制载波转换成IC卡使用的电源。

公开(公告)号：US5337063A

公开(公告)日：1994-08-09

申请号：US867538

申请日：1992-04-13

申请人： Kenichi Takahira

发明人： Kenichi Takahira

IPC分类号： B42D15/10 ,  G06K7/00 ,  G06K19/07 ,  G06K19/077 ,  H01Q1/22 ,  H01Q1/24 ,  H01Q1/36 ,  H01Q7/00 ,  H01Q11/12

CPC分类号： H01Q1/2225 ,  G06K19/0723 ,  G06K19/0726 ,  G06K19/07749 ,  G06K19/0775 ,  G06K19/07779 ,  G06K19/07783 ,  G06K7/0008 ,  H01Q1/22 ,  H01Q1/36 ,  H01Q7/00

摘要： An antenna circuit for a non-contact IC card exchanges signals with an external device utilizing electromagnetic waves. The antenna circuit includes a coil and a capacitor connected to form a resonant circuit. The coil includes a main coil having a spiral conductive pattern disposed on a peripheral portion of a substrate and a plurality of adjusting patterns, each electrically connecting a portion of the conductive pattern corresponding to a desired number of turns of the main coil to an end of the main coil. The plurality of adjusting patterns are disconnected from the main coil, except for one adjusting pattern, to obtain a coil of desired inductance.

摘要翻译： 用于非接触式IC卡的天线电路利用电磁波与外部设备交换信号。 天线电路包括线圈和电容器，连接形成谐振电路。 线圈包括具有布置在基板的周边部分上的螺旋导电图案的主线圈和多个调节图案，每个调整图案将导电图案的与主线圈的期望匝数相对应的一部分电连接到 主线圈。 除了一个调整图案之外，多个调整图案与主线圈断开，以获得所需电感的线圈。

公开(公告)号：US5056089A

公开(公告)日：1991-10-08

申请号：US306565

申请日：1989-02-06

申请人： Shigeru Furuta ,  Kenichi Takahira ,  Atsuo Yamaguchi ,  Takesi Inoue ,  Toshiyuki Matsubara ,  Shuzo Fujioka

发明人： Shigeru Furuta ,  Kenichi Takahira ,  Atsuo Yamaguchi ,  Takesi Inoue ,  Toshiyuki Matsubara ,  Shuzo Fujioka

IPC分类号： G06F11/08 ,  G06F11/10 ,  G06F11/267

CPC分类号： G06F11/2215 ,  G06F11/1008 ,  G06F11/1076

摘要： A memory system storing data detects and corrects an error in the stored data. The memory device includes a coding circuit for generating a systematic code including a data word and an error checking and correcting (ECC) code when the data word is supplied from a data bus during data writing, a memory cell array for storing the systematic code, and a sense amplifier for reading the systematic code from the memory cell. An error checking and correcting system generates a syndrome from the systematic code, decodes the syndrome to determine whether an error exists, identifies a bit position at which an error has occurred, and corrects the error contained in the data word by inverting a bit of the data word in the position at which the error has occured. The system includes a multiplexer for outputting the corrected data word to the data bus and a code reading circuit, for example, an ECC code register, for reading the ECC code generated by the coding circuit directly into the data bus. With this arrangement, it is possible to immediately and independently check the function of the coding circuit without influence from the memory cell array.

摘要翻译： 存储数据的存储器系统检测并校正所存储的数据中的错误。 存储装置包括编码电路，用于在数据写入期间从数据总线提供数据字时产生包括数据字和错误校验（ECC）码的系统码，用于存储系统码的存储单元阵列， 以及用于从存储器单元读取系统代码的读出放大器。 错误检查和校正系统从系统代码产生校正子，解码校验子以确定是否存在错误，识别发生错误的位位置，并且通过反转数据字中的位来校正数据字中包含的错误 发生错误的位置的数据字。 该系统包括用于将校正的数据字输出到数据总线的多路复用器和用于将由编码电路产生的ECC代码直接读入数据总线的代码读取电路，例如ECC代码寄存器。 利用这种布置，可以立即独立地检查编码电路的功能，而不受存储单元阵列的影响。

公开(公告)号：US4960982A

公开(公告)日：1990-10-02

申请号：US178551

申请日：1988-04-07

申请人： Kenichi Takahira

发明人： Kenichi Takahira

IPC分类号： G06K17/00 ,  G06K19/073 ,  G07F7/10

CPC分类号： G07F7/1008 ,  G06Q20/341 ,  G06Q20/3576 ,  G06Q20/367 ,  G06Q20/40975

摘要： An information recording system utilizing an IC card having an onboard microprocessor, an onboard semiconductor memory which can be accessed from outside the card only by way of the microprocessor, and an onboard mass storage device also accessible from outside the card but directly rather than through the microprocessor. The mass storage device can be a mass storage magnetic recording media or preferably an optical storage device, and provides a relatively inexpensive information storage media for large amounts of data. The semiconductor memory stores information which is necessary to properly access the information in the mass storage memory, and outputs that information to an associated interface unit only by way of the microprocessor. Thus, address or encryption information which is stored in the semiconductor memory is secure because of access being limited by the onboard microprocessor, and securing that information makes more secure the information stored in the mass storage device.

摘要翻译： 一种使用具有板载微处理器的IC卡的信息记录系统，仅能通过微处理器从卡外部访问的车载半导体存储器以及也可从卡外部直接而不是直接通过 微处理器。 大容量存储设备可以是大容量存储磁记录介质，或者优选地是光学存储设备，并且为大量数据提供相对便宜的信息存储介质。 半导体存储器存储正确访问大容量存储器中的信息所必需的信息，并且仅通过微处理器将该信息输出到关联的接口单元。 因此，存储在半导体存储器中的地址或加密信息是安全的，因为访问被板载微处理器限制，并且确保该信息使得存储在大容量存储设备中的信息更加安全。

公开(公告)号：US5191192A

公开(公告)日：1993-03-02

申请号：US756428

申请日：1991-09-09

申请人： Kenichi Takahira ,  Kazuo Asami

发明人： Kenichi Takahira ,  Kazuo Asami

IPC分类号： G06K19/07 ,  G07C9/00

CPC分类号： G06K19/0723 ,  G07C9/00111

摘要： A non-contact type information card includes a modulating/demodulating circuit, an antenna circuit, a CPU, a RAM, and a clock signal generating circuit. In the non-contact type information card, when the modulating/demodulating circuit receives a new command signal, the CPU determines whether first and second identification information in the new command signal agrees with the first and second identification information in an old command signal. When the first and second identification information of the new command signal agree with that of the old command signal, the CPU stops the operation of the clock generating circuit until the next command signal is received.

公开(公告)号：US5157247A

公开(公告)日：1992-10-20

申请号：US617009

申请日：1990-11-21

申请人： Kenichi Takahira

发明人： Kenichi Takahira

IPC分类号： B42D15/10 ,  G06K19/07

CPC分类号： G06K19/0723

摘要： An IC card has a data transmission/receiving circuit for exchanging data with an external device, a data processing circuit connected to the data transmission/receiving circuit for processing the data, a battery for supplying the data transmission/receiving circuit and the data processing circuit with electrical power, a charge storage device such as a capacitor charged at a predetermined time constant by the battery, a charge control circuit for controlling connection of the battery to the charge storage device in accordance with a control signal from the data processing circuit, a comparator circuit for comparing the output voltage from the charge storage device with a reference value, and a time measuring counter for measuring the time from electrical connection of the battery to the charge storage device until the comparator circuit detects an output voltage from the charge storage circuit exceeding the reference value.

公开(公告)号：US4992651A

公开(公告)日：1991-02-12

申请号：US178577

申请日：1988-04-07

申请人： Kenichi Takahira

发明人： Kenichi Takahira

IPC分类号： B42D15/10 ,  G06F12/02 ,  G06K19/07 ,  G07C1/10 ,  G07F7/10

CPC分类号： G07F7/1008 ,  G06F12/023 ,  G06Q20/341 ,  G06Q20/3552 ,  G07C1/10 ,  G07F7/084

摘要： A method of organizing time sequential application data in an IC card, and an IC card having a structure for organizing such time sequential data. The IC card has an onboard microprocessor and an onboard semiconductor memory. Information is recorded in addressable application blocks defined for the purpose of receiving and recording application data. So long as unrecorded information blocks remain available, new application data is recorded in time sequential locations in those blocks and a record is kept of the sequence of recordation along with the block address at which the data is recorded. When all of the application blocks are filed, the last mentioned record is searched to determine the oldest data recorded in an application block, the new data is overwritten over that data, and the time sequential record updated. The time sequential record of data allows the onboard microprocessor to determine locations in its associated memory where data is to be stored independently of the application program while still allowing the application program to access the data at locations which are, in effect, unknown to the application program.

摘要翻译： 一种在IC卡中组织时间序列应用数据的方法，以及具有用于组织这种时间序列数据的结构的IC卡。 IC卡具有板载微处理器和板上半导体存储器。 信息记录在为了接收和记录应用程序数据而定义的可寻址应用程序块中。 只要未记录的信息块保持可用，新的应用数据被记录在这些块中的时间顺序位置中，并且记录记录序列以及记录数据的块地址的记录。 当所有应用程序块被归档时，搜索最后提到的记录以确定记录在应用程序块中的最早的数据，新的数据被覆盖在该数据上，并且时间顺序记录被更新。 数据的时间顺序记录允许板载微处理器确定其相关存储器中的位置，其中数据将独立于应用程序存储，同时仍然允许应用程序在实际上是应用程序未知的位置访问数据 程序。

公开(公告)号：US4930129A

公开(公告)日：1990-05-29

申请号：US166624

申请日：1988-03-11

申请人： Kenichi Takahira

发明人： Kenichi Takahira

IPC分类号： B42D15/02 ,  B42D15/10 ,  G06F11/10 ,  G06K7/00 ,  G06K19/07 ,  G06K19/073 ,  G07F7/10

CPC分类号： G07F7/1008 ,  G06F11/1004 ,  G06K7/0008 ,  G06Q20/341 ,  G06Q20/35765 ,  G07F7/084

摘要： An IC card particularly adapted for multiple functions and having an error checking capability which operates within the card and without the need for the processing power of the terminal. The IC card has an onboard memory and an onboard microprocessor. The onboard memory contains a plurality of application blocks to which access is selectively allowed by the microprocessor and a protected block which is accessible by the microprocessor but inaccessible by the terminal. Stored within the protected block are data specifying the location, size and application associated with each of the application blocks, as well as an error check code relating to the data then stored within the application block.

摘要翻译： 一种特别适用于多种功能并且具有在卡内操作并且不需要终端的处理能力的错误检查能力的IC卡。 IC卡具有板载存储器和板载微处理器。 板载存储器包含多个应用程序块，微处理器选择性地允许访问，而受保护的程序块可由微处理器访问，但不能被终端访问。 存储在受保护块内的是指定与每个应用块相关联的位置，大小和应用的数据，以及与应用块中存储的数据相关的错误校验码。

公开(公告)号：US4924465A

公开(公告)日：1990-05-08

申请号：US260021

申请日：1988-10-20

申请人： Toshiyuki Matsubara ,  Shuzo Fujioka ,  Atsuo Yamaguchi ,  Kenichi Takahira ,  Shigeru Furuta ,  Takesi Inoue

发明人： Toshiyuki Matsubara ,  Shuzo Fujioka ,  Atsuo Yamaguchi ,  Kenichi Takahira ,  Shigeru Furuta ,  Takesi Inoue

IPC分类号： G06F12/16 ,  G06F11/10 ,  G06F11/267

CPC分类号： G06F11/2215 ,  G06F11/1008

摘要： A memory device for detecting and correcting errors in stored data includes a circuit for generating an error-detection/correction code with respect to data to be stored, a memory cell array in which the data and the error-detection/correction code are stored, an error-detection/correction circuit for detecting and corrrecting errors in the data by using the error-detection/correction code when the data is read out of the memory cell array, and a function test circuit selectively and directly connected to the error-detection/correction circuit for testing the error-detection/correction circuit.

摘要翻译： 用于检测和校正存储数据中的错误的存储装置包括用于产生关于要存储的数据的错误检测/校正码的电路，存储有数据和错误检测/校正码的存储单元阵列， 一个错误检测/校正电路，用于当数据从存储单元阵列读出时，通过使用错误检测/校正码来检测和校正数据中的错误;以及功能测试电路，选择性地和直接地连接到错误检测 /校正电路，用于测试误差检测/校正电路。