利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

17 条记录 (耗时 0.026 秒)

    Motor proteins and methods for their use
    5.
    发明授权
    Motor proteins and methods for their use 失效
    运动蛋白及其使用方法

    公开(公告)号：US06355466B1

    公开(公告)日：2002-03-12

    申请号：US09572191

    申请日：2000-05-17

    申请人： Christophe Beraud ,  Roman Sakowicz ,  Kenneth W. Wood

    发明人： Christophe Beraud ,  Roman Sakowicz ,  Kenneth W. Wood

    IPC分类号： C12N916

    CPC分类号： C07K14/475

    摘要： The invention provides isolated nucleic acid and amino acid sequences of HsKif15, antibodies to HsKif15, methods of screening for HsKif15 modulators using biologically active HsKif15, and kits for screening for HsKif15 modulators.

    摘要翻译： 本发明提供HsKif15的分离的核酸和氨基酸序列，HsKif15的抗体，使用生物活性HsKif15筛选HsKif15调节剂的方法，以及用于筛选HsKif15调节剂的试剂盒。

    Digital data processor for multiplying data by a coefficient set
    6.
    发明授权
    Digital data processor for multiplying data by a coefficient set 失效
    数字数据处理器，用于将数据乘以系数组

    公开(公告)号：US4701876A

    公开(公告)日：1987-10-20

    申请号：US651312

    申请日：1984-09-17

    申请人： John V. McCanny ,  John G. McWhirter ,  Kenneth W. Wood

    发明人： John V. McCanny ,  John G. McWhirter ,  Kenneth W. Wood

    IPC分类号： G06F15/16 ,  G06F15/80 ,  G06F17/15 ,  G06F15/336 ,  G06F15/347

    CPC分类号： G06F15/8046 ,  G06F17/15

    摘要： A digital data processor is provided to multiply data elements by coefficients. It includes a systolic array of cells consisting of nearest neighbor connected gated full adders. The cells multiply data bits received from laterally adjacent cells and subsequently pass them on. The product is added to a cumulative sum bit from a cell above and to a carry bit recirculated from an earlier computation. The output is passed to a cell below, and a new carry bit is recirculated for addition in a subsequent computation. Data and coefficients are input in counterflow to opposite sides of the array. An adder tree accumulates non-simultaneously computed contributions to individual output terms. The tree incorporates a delay and switches arranged to implement or bypass the delay according to earlier or later computation of a contribution. By virtue of this accumulation, the processor provides reduced cell redundancy compared to the prior art.

    摘要翻译： 提供数字数据处理器以通过系数乘以数据元素。 它包括由最近邻接的门控全加法器组成的心脏收缩阵列。 这些单元将从横向相邻单元接收的数据位进行乘法，并随后将其传递。 将乘积加到上一个单元的累加和位和从较早计算中循环的进位位。 输出被传递到下面的一个单元格，并且一个新的进位位被再循环以便在随后的计算中加法。 数据和系数以逆流方式输入到阵列的相对侧。 加法器树将非同时计算的贡献累加到各个输出项。 该树结合了延迟，并且被布置为根据贡献的更早或更晚的计算实现或绕过延迟。 凭借这种积累，与现有技术相比，处理器提供了减小的单元冗余。

    Pipelined systolic array for matrix-matrix multiplication
    7.
    发明授权
    Pipelined systolic array for matrix-matrix multiplication 失效
    用于矩阵矩阵乘法的流水线收缩阵列

    公开(公告)号：US4686645A

    公开(公告)日：1987-08-11

    申请号：US639423

    申请日：1984-08-10

    申请人： John V. McCanny ,  John G. McWhirter ,  Kenneth W. Wood

    发明人： John V. McCanny ,  John G. McWhirter ,  Kenneth W. Wood

    IPC分类号： G06F17/16 ,  G06F15/80 ,  G06F7/52

    CPC分类号： G06F15/8046

    摘要： A digital data processor for matrix/matrix multiplication includes a systolic array of nearest neighbor connected gated full adders. The adders are arranged to multiply two input data bits and to add their product to an input cumulative sum bit and a carry bit from a lower order bit computation. The result and input data bits are output to respective neighboring cells, a new carry bit being recirculated for later addition to a higher order bit computation. Column elements of one matrix and row elements of the other are input to either side of the array bit-serially, least significant bit leading, for mutual counterpropagation therethrough with a cumulative time delay between input of adjacent columns or rows. Bit-level matrix interactions for product matrix computation occur at individual cells. Pairs of intercalated adder trees are connected switchably to the array to accumulate bit-level contributions to product matrix elements.

    摘要翻译： 用于矩阵/矩阵乘法的数字数据处理器包括最近邻连接门控全加器的收缩阵列。 加法器被布置为将两个输入数据位相乘并将它们的乘积加到来自较低阶位计算的输入累积和位和进位位。 结果和输入数据位被输出到相应的相邻单元，一个新的进位位被再循环以供稍后添加到更高阶位计算。 将一个矩阵的列元素和另一个的行元素的列元素输入到阵列的任一侧，位串联，最低有效位引导，用于相互反向传播，其中相邻列或行的输入之间的累积时间延迟。 产品矩阵计算的位级矩阵相互作用发生在单个单元格中。 插入加法器树的对可切换地连接到阵列以累积对产品矩阵元素的位级贡献。