公开(公告)号：US5898867A

公开(公告)日：1999-04-27

申请号：US132410

申请日：1993-10-06

申请人： Klaus Joerg Getzlaff ,  Johann Hajdu, deceased ,  Brigitte Roethe ,  Udo Wille

发明人： Klaus Joerg Getzlaff ,  Johann Hajdu, deceased ,  Brigitte Roethe ,  Udo Wille

IPC分类号： G06F9/22 ,  G06F9/24 ,  G06F9/26 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F12/08 ,  G06F12/16

CPC分类号： G06F9/268 ,  G06F11/1028 ,  G06F11/141 ,  G06F9/24 ,  G06F9/26 ,  G06F9/328 ,  G06F11/1008

摘要： A multiprocessor computer system includes a system clock, a main memory connected through a memory bus to a microinstruction memory and a microinstruction decoder. Circuitry detects whether the microinstruction being decoded is the wrong microinstruction or has a parity error. On detection of such an erroneous microinstruction, the microinstruction is reloaded from the main memory into the microinstruction memory and then passed to the microinstruction decoder without interrupting the system clock or operation of the other processors.

摘要翻译： 多处理器计算机系统包括系统时钟，通过存储器总线连接到微指令存储器的主存储器和微指令解码器。 电路检测是否正在解码的微指令是错误的微指令还是具有奇偶校验错误。 在检测到这种错误的微指令时，微指令从主存储器重新加载到微指令存储器中，然后传递到微指令解码器，而不中断其他处理器的系统时钟或操作。

公开(公告)号：US5761521A

公开(公告)日：1998-06-02

申请号：US619496

申请日：1996-03-26

申请人： Herbert Chilinski ,  Klaus Joerg Getzlaff ,  Wilhelm Ernst Haller ,  Ralph Koester

发明人： Herbert Chilinski ,  Klaus Joerg Getzlaff ,  Wilhelm Ernst Haller ,  Ralph Koester

IPC分类号： G06F9/305 ,  G06F7/02 ,  G06F9/34 ,  G06F7/00

CPC分类号： G06F7/026

摘要： A processor for character strings A, B of variable length serves for the fast detection of match, mismatch and comparative difference conditions between them. The character strings, whose lengths are delimited by character string termination marks, are split into consecutive substrings with a byte count corresponding to the data path width, and processed to detect a match, a mismatch and an end-of-byte mark. Each substring is routed via operand registers (16,18) in parallel to an arithmetic unit (20), a logic unit (22) and a comparator unit (24) and simultaneously processed. The arithmetic unit (20) subtracts one substring from the other substring, the logic unit (22) compares both substrings with each other and the comparator unit (24) compares the bytes of both substrings with the contents of a marking register (26), previously set to the end-of-string mark. These operations are executed in one machine cycle. Output signals from the comparator unit serve to indicate the equality of both substrings, output signals from the logic unit serve to indicate the inequality of both substrings and a carry signal from the arithmetic unit serves at the same time to indicate which of the two substrings is the greater or the lesser.

摘要翻译： PCT No.PCT / EP94 / 03045 Sec。 371日期：1996年3月26日 102（e）1996年3月26日PCT PCT 1994年9月12日PCT公布。 WO95 / 10803 PCT出版物 日期1995年04月20日可变长度的字符串A，B的处理器用于快速检测它们之间的匹配，不匹配和比较差异条件。 长度由字符串终止符分隔的字符串被分割成与数据路径宽度相对应的字节数的连续子字符串，并被处理以检测匹配，不匹配和字节结尾标记。 每个子串通过操作数寄存器（16,18）并行地运算到运算单元（20），逻辑单元（22）和比较器单元（24）并同时处理。 算术单元（20）从另一个子串中减去一个子串，逻辑单元（22）将两个子串彼此进行比较，比较单元（24）将两个子串的字节与标记寄存器（26）的内容进行比较， 以前设置为字符串结束标记。 这些操作在一个机器周期中执行。 来自比较器单元的输出信号用于指示两个子串的相等，来自逻辑单元的输出信号用于指示两个子串的不等式，并且来自算术单元的进位信号同时工作以指示两个子串中的哪一个是 越来越大。

公开(公告)号：US5761734A

公开(公告)日：1998-06-02

申请号：US689762

申请日：1996-08-13

申请人： Erwin Pfeffer ,  Klaus-Joerg Getzlaff ,  Ute Gaertner ,  Hans-Werner Tast

发明人： Erwin Pfeffer ,  Klaus-Joerg Getzlaff ,  Ute Gaertner ,  Hans-Werner Tast

IPC分类号： G06F9/46 ,  G06F12/10 ,  G06F12/16

CPC分类号： G06F9/52 ,  G06F12/1072

摘要： A process is disclosed to serialize instructions that are to be processed serially in a multiprocessor system, with the use of a token, where the token can be assigned on request to one of the processors, which thereupon has the right to execute the command. If the command consists of dristibuted tasks, the token remains blocked until the last dependent task belonging to the command has also been executed. It is only then that the token can be assigned to another instruction. Moreover, a device is described to manage this token, which features three states: a first state, in which the token is available, a second state, in which the token is assigned to one of the processors, and a third state, in which the token is blocked, because dependent tasks still have to be carried out. Moreover, a circuit is disclosed with which the token principle that is introduced can be implemented in a simple manner. The token is only available if none of the processors i is in possession of the token and if no dependent task is pending at any of the processors. The OR chaining of signals to form a signal C which is set if the token is not available represents the basic circuitry with which the serialisation of commands consisting of distributed tasks is carried out. The invention is applied particularly in the case of commands such as IPTE (invalidate page-table entry) and SSKE (set storage key extended), which modify the address translation tables in the memory that are used in common by all processors.

摘要翻译： 公开了一种过程，其使用令牌来序列化要在多处理器系统中串行处理的指令，其中令牌可以根据请求分配给一个处理器，其中有一个执行命令。 如果命令由dristibuted任务组成，令牌将保持阻塞，直到属于命令的最后一个任务也已被执行。 只有令牌可以分配给另一个指令。 此外，描述了一种用于管理该令牌的设备，其特征在于三个状态：其中令牌可用的第一状态，其中将令牌分配给处理器之一的第二状态和第三状态，其中 令牌被阻止，因为依赖的任务仍然需要执行。 此外，公开了可以以简单的方式实现引入的令牌原理的电路。 该令牌仅在没有任何一个处理器拥有该令牌并且任何一个处理器中未依赖任务的情况下可用。 如果令牌不可用，则形成信号C的OR链接形成表示执行由分散任务组成的命令的串行化的基本电路。 本发明特别适用于诸如IPTE（无效页表条目）和SSKE（设置存储密钥扩展）的命令的情况，其修改由所有处理器共同使用的存储器中的地址转换表。