公开(公告)号：US07985675B2

公开(公告)日：2011-07-26

申请号：US12251984

申请日：2008-10-15

Applicant: Kotaro Nomura ,  Makoto Tsutsue

Inventor： Kotaro Nomura ,  Makoto Tsutsue

IPC: H01L21/4763

CPC classification number: H01L23/53238 ,  H01L21/76822 ,  H01L21/76825 ,  H01L21/76828 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes: a semiconductor substrate; a first insulating film (third insulating film 24) formed on the semiconductor substrate, having a first trench (second interconnect trench 28), and having a composition ratio varying along the depth from an upper face of the first insulating film; and a first metal interconnect (second metal interconnect 25) filling the first trench (second interconnect trench 28). The mechanical strength in an upper portion of the first insulating film (third insulating film 24) is higher than that in the other portion of the insulating film (third insulating film 24).

Abstract translation: 半导体器件包括：半导体衬底; 形成在所述半导体基板上的第一绝缘膜（第三绝缘膜24），具有第一沟槽（第二互连沟槽28），并且具有从所述第一绝缘膜的上表面沿深度变化的组成比; 以及填充第一沟槽（第二互连沟槽28）的第一金属互连（第二金属互连25）。 第一绝缘膜（第三绝缘膜24）的上部的机械强度高于绝缘膜（第三绝缘膜24）的其他部分的机械强度。

公开(公告)号：US20110081776A1

公开(公告)日：2011-04-07

申请号：US12822782

申请日：2010-06-24

Applicant: Kotaro NOMURA ,  Makoto Tsutsue

Inventor： Kotaro NOMURA ,  Makoto Tsutsue

IPC: H01L21/768

CPC classification number: H01L21/76832 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76834

Abstract: A first insulating film is formed on or above a substrate, and a first conductor is formed in an upper portion of the formed first insulating film. Then, a second insulating film is formed on the first insulating film so as to cover the first conductor. Then, a film quality alteration process is performed for the second insulating film. Moreover, a third insulating film is formed on the second insulating film, and a curing process is performed for the formed third insulating film.

Abstract translation: 第一绝缘膜形成在基板上或上方，并且第一导体形成在所形成的第一绝缘膜的上部。 然后，在第一绝缘膜上形成覆盖第一导体的第二绝缘膜。 然后，对第二绝缘膜进行膜质量改变处理。 此外，在第二绝缘膜上形成第三绝缘膜，对所形成的第三绝缘膜进行固化处理。

公开(公告)号：US20120007257A1

公开(公告)日：2012-01-12

申请号：US13243011

申请日：2011-09-23

Applicant: Kotaro NOMURA

Inventor： Kotaro NOMURA

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02271 ,  H01L21/3105 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76835 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes: a first insulating film formed on a substrate and having a first interconnect; a second insulating film as a liner film formed on the first insulating film and the first interconnect so as to contact the first insulating film; and a third insulating film formed on the second insulating film so as to contact the second insulating film. The second insulating film includes pores.

Abstract translation: 半导体器件包括：形成在基板上并具有第一互连的第一绝缘膜; 形成在所述第一绝缘膜和所述第一互连件上以与所述第一绝缘膜接触的作为衬垫膜的第二绝缘膜; 以及形成在第二绝缘膜上以与第二绝缘膜接触的第三绝缘膜。 第二绝缘膜包括孔。

公开(公告)号：US20080093709A1

公开(公告)日：2008-04-24

申请号：US11907998

申请日：2007-10-19

Applicant: Masazumi Matsuura ,  Kinya Goto ,  Hisashi Yano ,  Kotaro Nomura

Inventor： Masazumi Matsuura ,  Kinya Goto ,  Hisashi Yano ,  Kotaro Nomura

IPC: H01L21/42 ,  H01L23/58

CPC classification number: H01L21/428 ,  H01L29/78

Abstract: A semiconductor substrate in a state that an inter-layer insulation film is formed is loaded in a chamber, air in the chamber is purged by introducing a large amount of a nitrogen gas in the chamber, and an atmospheric gas in the chamber is substituted with a nitrogen gas. After that, UV cure is performed by introducing a small amount of an oxygen gas adjusted to an atmospheric pressure or a little more positive pressure in the chamber by nitrogen purge. For the introduction of an oxygen gas, an oxygen gas is introduced while controlling the flow rate by using a flow meter, and adjustment is performed using the flow meter so that the oxygen concentration in the chamber becomes a constant value in the range of 5 ppm to 400 ppm.

Abstract translation: 将形成有层间绝缘膜的状态的半导体基板载置在室内，通过在室内引入大量的氮气来吹扫室内的空气，将室内的气氛气体置换为 氮气。 之后，通过氮气吹扫在腔室内引入少量调节至大气压或稍微正压的氧气来进行UV固化。 为了引入氧气，引入氧气，同时通过使用流量计来控制流量，并且使用流量计进行调节，使得室中的氧浓度变为在5ppm范围内的恒定值 至400ppm。

公开(公告)号：US07795133B2

公开(公告)日：2010-09-14

申请号：US12332392

申请日：2008-12-11

Applicant: Kotaro Nomura

Inventor： Kotaro Nomura

IPC: H01L21/4763

CPC classification number: H01L23/5226 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76822 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: By covering inner surfaces of a wiring groove 26c and a via hole 27a with a fourth insulation film 25 containing porogen during a manufacturing process of a semiconductor device, an increase in the relative permittivity of the fourth insulation film 25 that is a low-permittivity film on the inner surfaces of the wiring groove 26c and the via hole 27a can be suppressed in a manufacturing process of a semiconductor device such as a barrier metal sputtering process.

Abstract translation: 通过在半导体器件的制造过程中，通过在包含致孔剂的第四绝缘膜25上覆盖布线槽26c和通孔27a的内表面，作为低介电常数膜的第四绝缘膜25的相对介电常数的增加 在诸如阻挡金属溅射工艺的半导体器件的制造工艺中，可以抑制布线槽26c和通孔27a的内表面。

公开(公告)号：US20090152732A1

公开(公告)日：2009-06-18

申请号：US12332392

申请日：2008-12-11

Applicant: Kotaro Nomura

Inventor： Kotaro Nomura

IPC: H01L23/52 ,  H01L21/4763

CPC classification number: H01L23/5226 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76822 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: By covering inner surfaces of a wiring groove 26c and a via hole 27a with a fourth insulation film 25 containing porogen during a manufacturing process of a semiconductor device, an increase in the relative permittivity of the fourth insulation film 25 that is a low-permittivity film on the inner surfaces of the wiring groove 26c and the via hole 27a can be suppressed in a manufacturing process of a semiconductor device such as a barrier metal sputtering process.

Abstract translation: 通过在半导体器件的制造过程中，通过在包含致孔剂的第四绝缘膜25上覆盖布线槽26c和通孔27a的内表面，作为低介电常数膜的第四绝缘膜25的相对介电常数的增加 在诸如阻挡金属溅射工艺的半导体器件的制造工艺中，可以抑制布线槽26c和通孔27a的内表面。

公开(公告)号：US20090121359A1

公开(公告)日：2009-05-14

申请号：US12251984

申请日：2008-10-15

Applicant: Kotaro Nomura ,  Makoto Tsutsue

Inventor： Kotaro Nomura ,  Makoto Tsutsue

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/76822 ,  H01L21/76825 ,  H01L21/76828 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes: a semiconductor substrate; a first insulating film (third insulating film 24) formed on the semiconductor substrate, having a first trench (second interconnect trench 28), and having a composition ratio varying along the depth from an upper face of the first insulating film; and a first metal interconnect (second metal interconnect 25) filling the first trench (second interconnect trench 28). The mechanical strength in an upper portion of the first insulating film (third insulating film 24) is higher than that in the other portion of the insulating film (third insulating film 24).

Abstract translation: 半导体器件包括：半导体衬底; 形成在所述半导体基板上的第一绝缘膜（第三绝缘膜24），具有第一沟槽（第二互连沟槽28），并且具有从所述第一绝缘膜的上表面沿深度变化的组成比; 以及填充第一沟槽（第二互连沟槽28）的第一金属互连（第二金属互连25）。 第一绝缘膜（第三绝缘膜24）的上部的机械强度高于绝缘膜（第三绝缘膜24）的其他部分的机械强度。