公开(公告)号：US07985675B2

公开(公告)日：2011-07-26

申请号：US12251984

申请日：2008-10-15

申请人： Kotaro Nomura ,  Makoto Tsutsue

发明人： Kotaro Nomura ,  Makoto Tsutsue

IPC分类号： H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/76822 ,  H01L21/76825 ,  H01L21/76828 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: a semiconductor substrate; a first insulating film (third insulating film 24) formed on the semiconductor substrate, having a first trench (second interconnect trench 28), and having a composition ratio varying along the depth from an upper face of the first insulating film; and a first metal interconnect (second metal interconnect 25) filling the first trench (second interconnect trench 28). The mechanical strength in an upper portion of the first insulating film (third insulating film 24) is higher than that in the other portion of the insulating film (third insulating film 24).

摘要翻译： 半导体器件包括：半导体衬底; 形成在所述半导体基板上的第一绝缘膜（第三绝缘膜24），具有第一沟槽（第二互连沟槽28），并且具有从所述第一绝缘膜的上表面沿深度变化的组成比; 以及填充第一沟槽（第二互连沟槽28）的第一金属互连（第二金属互连25）。 第一绝缘膜（第三绝缘膜24）的上部的机械强度高于绝缘膜（第三绝缘膜24）的其他部分的机械强度。

公开(公告)号：US20110081776A1

公开(公告)日：2011-04-07

申请号：US12822782

申请日：2010-06-24

申请人： Kotaro NOMURA ,  Makoto Tsutsue

发明人： Kotaro NOMURA ,  Makoto Tsutsue

IPC分类号： H01L21/768

CPC分类号： H01L21/76832 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76834

摘要： A first insulating film is formed on or above a substrate, and a first conductor is formed in an upper portion of the formed first insulating film. Then, a second insulating film is formed on the first insulating film so as to cover the first conductor. Then, a film quality alteration process is performed for the second insulating film. Moreover, a third insulating film is formed on the second insulating film, and a curing process is performed for the formed third insulating film.

摘要翻译： 第一绝缘膜形成在基板上或上方，并且第一导体形成在所形成的第一绝缘膜的上部。 然后，在第一绝缘膜上形成覆盖第一导体的第二绝缘膜。 然后，对第二绝缘膜进行膜质量改变处理。 此外，在第二绝缘膜上形成第三绝缘膜，对所形成的第三绝缘膜进行固化处理。

公开(公告)号：US20090121359A1

公开(公告)日：2009-05-14

申请号：US12251984

申请日：2008-10-15

申请人： Kotaro Nomura ,  Makoto Tsutsue

发明人： Kotaro Nomura ,  Makoto Tsutsue

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L23/53238 ,  H01L21/76822 ,  H01L21/76825 ,  H01L21/76828 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: a semiconductor substrate; a first insulating film (third insulating film 24) formed on the semiconductor substrate, having a first trench (second interconnect trench 28), and having a composition ratio varying along the depth from an upper face of the first insulating film; and a first metal interconnect (second metal interconnect 25) filling the first trench (second interconnect trench 28). The mechanical strength in an upper portion of the first insulating film (third insulating film 24) is higher than that in the other portion of the insulating film (third insulating film 24).

摘要翻译： 半导体器件包括：半导体衬底; 形成在所述半导体基板上的第一绝缘膜（第三绝缘膜24），具有第一沟槽（第二互连沟槽28），并且具有从所述第一绝缘膜的上表面沿深度变化的组成比; 以及填充第一沟槽（第二互连沟槽28）的第一金属互连（第二金属互连25）。 第一绝缘膜（第三绝缘膜24）的上部的机械强度高于绝缘膜（第三绝缘膜24）的其他部分的机械强度。

公开(公告)号：US08564136B2

公开(公告)日：2013-10-22

申请号：US13038974

申请日：2011-03-02

申请人： Makoto Tsutsue

发明人： Makoto Tsutsue

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L23/5329 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/7682 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes an interlayer dielectric with a single-layer structure having a plurality of pores. The porosity of the interlayer dielectric per unit volume varies in a thickness direction.

摘要翻译： 半导体器件包括具有多个孔的单层结构的层间电介质。 每单位体积的层间电介质的孔隙率在厚度方向上变化。

公开(公告)号：US07994589B2

公开(公告)日：2011-08-09

申请号：US12858942

申请日：2010-08-18

申请人： Makoto Tsutsue ,  Masaki Utsumi

发明人： Makoto Tsutsue ,  Masaki Utsumi

IPC分类号： H01L29/76

CPC分类号： H01L23/585 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/562 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.

公开(公告)号：US07795705B2

公开(公告)日：2010-09-14

申请号：US12210520

申请日：2008-09-15

申请人： Makoto Tsutsue

发明人： Makoto Tsutsue

IPC分类号： H01L23/544

CPC分类号： H01L23/585 ,  H01L21/768 ,  H01L21/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes an element formed on a substrate, at least one insulating film formed on the substrate, and a seal ring formed in the insulating film so as to surround a region where the element is formed and to extend through the insulating film. The semiconductor device further includes a void region including a void and formed in the insulating film in a region located outside the seal ring when viewed from the element.

摘要翻译： 半导体器件包括形成在衬底上的元件，在衬底上形成的至少一个绝缘膜，以及形成在绝缘膜中的密封环，以围绕元件形成的区域并延伸穿过绝缘膜。 半导体器件还包括空隙区域，该空隙区域在从元件观察时位于密封环外侧的区域中形成在绝缘膜中。

公开(公告)号：US08247876B2

公开(公告)日：2012-08-21

申请号：US13171181

申请日：2011-06-28

申请人： Makoto Tsutsue ,  Masaki Utsumi

发明人： Makoto Tsutsue ,  Masaki Utsumi

IPC分类号： H01L29/66

CPC分类号： H01L23/585 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/562 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.

摘要翻译： 通过在芯片区域的外围部分中的多个电介质膜的多层结构形成密封环结构，以围绕芯片区域。 在芯片区域中的至少一个电介质膜中形成双组件镶嵌互连，其中互连和连接到互连的插头被集成。 在其中形成双镶嵌互连的电介质膜中形成的密封环结构的一部分是连续的。 形成在多层结构上的保护膜在密封环上具有开口。 连接到密封环的盖层形成在开口中。

公开(公告)号：US20060076651A1

公开(公告)日：2006-04-13

申请号：US11223943

申请日：2005-09-13

申请人： Makoto Tsutsue

发明人： Makoto Tsutsue

IPC分类号： H01L21/30 ,  H01L23/544

CPC分类号： H01L23/585 ,  H01L21/78 ,  H01L23/562 ,  H01L23/564 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： An electronic device has an element formed in the chip region of a substrate, a plurality of interlayer insulating films formed on the substrate, a wire formed in the interlayer insulating films in the chip region, and a plug formed in the interlayer insulating films in the chip region and connecting to the wire. A seal ring extending through the plurality of interlayer insulating films and continuously surrounding the chip region is formed in the peripheral portion of the chip region. A stress absorbing wall extending through the plurality of interlayer insulating films and discretely surrounding the seal ring is formed outside the seal ring.

摘要翻译： 电子器件具有形成在衬底的芯片区域中的元件，在衬底上形成的多个层间绝缘膜，在芯片区域中的层间绝缘膜中形成的导线，以及形成在芯片区域中的层间绝缘膜中的插塞 芯片区域并连接到电线。 在芯片区域的周边部分形成有延伸穿过多个层间绝缘膜并连续围绕芯片区域的密封环。 在密封环的外部形成有延伸穿过多个层间绝缘膜并离散地围绕密封环的应力吸收壁。

公开(公告)号：US20050098893A1

公开(公告)日：2005-05-12

申请号：US10983760

申请日：2004-11-09

申请人： Makoto Tsutsue ,  Masaki Utsumi

发明人： Makoto Tsutsue ,  Masaki Utsumi

IPC分类号： H01L23/00 ,  H01L23/522 ,  H01L23/58 ,  H01L23/48

CPC分类号： H01L23/585 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/562 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.

摘要翻译： 通过在芯片区域的外围部分中的多个电介质膜的多层结构形成密封环结构，以围绕芯片区域。 在芯片区域中的至少一个电介质膜中形成双组件镶嵌互连，其中互连和连接到互连的插头被集成。 在其中形成双镶嵌互连的电介质膜中形成的密封环结构的一部分是连续的。 形成在多层结构上的保护膜在密封环上具有开口。 连接到密封环的盖层形成在开口中。

公开(公告)号：US08508002B2

公开(公告)日：2013-08-13

申请号：US13551425

申请日：2012-07-17

申请人： Makoto Tsutsue ,  Masaki Utsumi

发明人： Makoto Tsutsue ,  Masaki Utsumi

IPC分类号： H01L29/66

摘要： A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.