公开(公告)号：US20120072877A1

公开(公告)日：2012-03-22

申请号：US13229908

申请日：2011-09-12

申请人： Hideki TAKAHASHI ,  Tsuyoshi Etoh ,  Tomohito Kawano ,  Tatsuya Hiramatsu ,  Kiyoharu Murakami ,  Kouji Nakao

发明人： Hideki TAKAHASHI ,  Tsuyoshi Etoh ,  Tomohito Kawano ,  Tatsuya Hiramatsu ,  Kiyoharu Murakami ,  Kouji Nakao

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： According to one embodiment, a layout verification apparatus includes a design section, a layout creation section, a first verification section and a second verification section. One of the first and second verification sections includes a filter processing section which executes a filter processing of a verification target element to be verified by a mask data used to a manufacture of the semiconductor integrated circuit, and the verification target element to be verified needs an ion implantation. The filter processing section comprises a first logic section which executes an logical AND of the verification target element to be verified, a mask data necessary in order to form the verification target element to be verified, and a data inverted a mask data unnecessary in order to form the verification target element to be verified.

摘要翻译： 根据一个实施例，布局验证装置包括设计部分，布局创建部分，第一验证部分和第二验证部分。 第一和第二验证部分之一包括滤波处理部分，其执行将由用于制造半导体集成电路的掩模数据验证的验证目标元件的滤波处理，并且待验证的验证目标元件需要 离子注入。 滤波处理部分包括执行要验证的验证目标元件的逻辑与的第一逻辑部分，为了形成待验证的验证目标元件所必需的掩模数据，以及不需要的掩码数据的数据反转，以便 形成要验证的验证目标元素。

公开(公告)号：US06811200B2

公开(公告)日：2004-11-02

申请号：US10774433

申请日：2004-02-10

申请人： Keeichirou Shibata ,  Kouji Nakao ,  Kenji Satani ,  Masahiko Hondou

发明人： Keeichirou Shibata ,  Kouji Nakao ,  Kenji Satani ,  Masahiko Hondou

IPC分类号： B60N214

CPC分类号： B60N2/3029 ,  B60N2/01 ,  B60N2/3009 ,  B60N2/3018 ,  B60N2/3043 ,  B60N2/3086 ,  B60N2/757 ,  B60N2/79 ,  B60N2/835 ,  B60N2/891

摘要： A seat cushion comprises a cushion body portion including a storage recess and a cushion bottom portion covering the storage recess so as to selectively open or close it. A supplementary seat comprises a supplementary seat back which is pivotally supported so as to rotate in the longitudinal direction and a supplementary seat cushion formed separately from the supplementary seat back. The supplementary seat cushion is configured so as to selectively take a sitting position, where it is located at the side of the seat cushion, and a stored position, where it is stored in the storage recess. Accordingly, since only the supplementary seat cushion is stored in the storage recess, the deterioration of comfortable ride caused by the high-sitting point can be suppressed. Also, the supplementary seat back can be used as a armrest or the like.

摘要翻译： 座垫包括缓冲体部分，该缓冲体部分包括收纳凹部和覆盖该收纳凹部的缓冲底部，以选择性地打开或闭合该衬垫本体部。 辅助座椅包括被可枢转地支撑以沿纵向旋转的辅助座椅靠背和与辅助座椅靠背分开形成的辅助座垫。 辅助座垫被构造成选择性地坐在座位的座位上，并且存储在存储位置中，在那里存储在存储凹部中。因此，由于只有辅助座垫是 存储在存储凹部中，可以抑制由高坐标点引起的舒适乘坐的恶化。 此外，辅助座椅靠背可以用作扶手等。

公开(公告)号：US07151751B2

公开(公告)日：2006-12-19

申请号：US09954211

申请日：2001-09-18

申请人： Atsushi Tagami ,  Teruyuki Hasegawa ,  Toru Hasegawa ,  Kouji Nakao ,  Hiroki Furuya ,  Hajime Nakamura

发明人： Atsushi Tagami ,  Teruyuki Hasegawa ,  Toru Hasegawa ,  Kouji Nakao ,  Hiroki Furuya ,  Hajime Nakamura

IPC分类号： G01R31/08

CPC分类号： H04L43/50

摘要： Data of traffic with long-range dependence characteristics is generated by a host terminal and transferred to a memory arranged on a board. The memory stores the traffic data comprising at least one of the number of IP packets output per unit time and total number of bytes, a set value of each parameter of the generated IP packets (i.e., packet length table) and an IP address table. A packet generation section refers to the data in the memory to generate traffic with long-range dependence characteristics at a speed corresponding to a high-speed network. As a result, the behavior of the network at the time of application of the load can be measured before the actual use of the network. According to the present invention, a traffic generation apparatus that can supply the actual network with a load close to the real traffic can be provided.

摘要翻译： 具有长距离依赖特性的业务的数据由主机终端产生并传送到布置在电路板上的存储器。 存储器存储包括每单位时间输出的IP分组数量和总字节数，生成的IP分组的每个参数的设定值（即，分组长度表）和IP地址表中的至少一个的业务数据。 分组产生部分参考存储器中的数据，以对应于高速网络的速度产生具有长范围依赖特性的业务。 因此，在实际使用网络之前可以测量网络在应用负载时的行为。 根据本发明，可以提供能够向实际网络提供接近实际业务的负载的业务量生成装置。

公开(公告)号：US5487044A

公开(公告)日：1996-01-23

申请号：US372906

申请日：1995-01-17

申请人： Takayuki Kawaguchi ,  Shigeto Mizukami ,  Yasumitsu Nozawa ,  Kouji Nakao

发明人： Takayuki Kawaguchi ,  Shigeto Mizukami ,  Yasumitsu Nozawa ,  Kouji Nakao

IPC分类号： G11C11/41 ,  G11C7/12 ,  H01L27/10 ,  G11C7/00

CPC分类号： G11C7/12

摘要： A semiconductor memory device having memory cells arranged in a matrix, each of the memory cells having input/output terminals, word lines for selecting the memory cells, pairs of bit lines connected to the input/output terminals, bit line pulling-up means for pulling up the potential of the bit lines, bit line loading means connected to another pair of bit lines and bit line equalizing means provided for the bit lines for equalizing the potential of the bit lines by allowing conduction between the bit lines before data is read from a selected memory cell.

摘要翻译： 一种具有以矩阵形式布置的存储单元的半导体存储器件，每个存储器单元具有输入/输出端子，用于选择存储单元的字线，连接到输入/输出端子的位线对，位线提升装置， 提高位线的电位，连接到另一对位线的位线加载装置和为位线提供的位线均衡装置，用于通过在读取数据之前允许位线之间的导通来均衡位线的电位 选择的存储单元。

公开(公告)号：US5455795A

公开(公告)日：1995-10-03

申请号：US341418

申请日：1994-11-17

申请人： Kouji Nakao ,  Shigeto Mizukami

发明人： Kouji Nakao ,  Shigeto Mizukami

IPC分类号： G11C17/18 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  G11C11/41 ,  G11C16/02 ,  G11C17/00 ,  G11C13/00

CPC分类号： G11C7/1033

摘要： A semiconductor memory device comprises a page access mode, a plurality of sense amplifiers for detecting data read from a plurality of memory cells selected based on first address inputs A2 to An, a plurality of latch circuits for latching data from the plurality of sense amplifiers, a reading circuit for reading latch data based on second address inputs A0 and A1 corresponding to the plurality of latch circuits, and a control circuit for controlling the sense amplifier to be activated when only the first address input or both first and second address inputs are changed, and to be inactivated when only the second address input is changed.

摘要翻译： 半导体存储器件包括页访问模式，用于检测从基于第一地址输入A2至An所选择的多个存储单元读取的数据的多个读出放大器，用于锁存来自多个读出放大器的数据的多个锁存电路， 读取电路，用于基于与多个锁存电路相对应的第二地址输入A0和A1读取锁存数据;以及控制电路，用于当只有第一地址输入或第一和第二地址输入都被改变时控制读出放大器被激活 ，并且仅在第二地址输入改变时被禁用。