公开(公告)号：US08259493B2

公开(公告)日：2012-09-04

申请号：US12433173

申请日：2009-04-30

申请人： Hitoshi Ohta ,  Tomohito Kawano ,  Akira Umezawa

发明人： Hitoshi Ohta ,  Tomohito Kawano ,  Akira Umezawa

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C29/12 ,  G11C2029/1202 ,  G11C2029/1802

摘要： A nonvolatile semiconductor storage device includes a memory cell array including a plurality of memory cells arranged at intersection positions of word lines and bit lines in a matrix form, and a row decoder including a row sub-decoder to which a lower address for selecting a word line is input, wherein one unit of the row sub-decoder for selecting one word line is constituted of a first transistor of a first conduction type, and a second transistor of a second conduction type, and a gate electrode of each of the first and second transistors is arranged in a direction in which the bit lines are arranged.

摘要翻译： 非易失性半导体存储装置包括存储单元阵列，其包括以矩阵形式布置在字线和位线的交叉位置处的多个存储单元，以及行解码器，包括行子解码器，用于选择字的较低地址 行，其中用于选择一个字线的行子解码器的一个单元由第一导电类型的第一晶体管和第二导电类型的第二晶体管和第一和第二导体的第二晶体管构成， 第二晶体管沿排列位线的方向排列。

公开(公告)号：US07382670B2

公开(公告)日：2008-06-03

申请号：US11669420

申请日：2007-01-31

申请人： Tomohito Kawano ,  Hidetoshi Saito

发明人： Tomohito Kawano ,  Hidetoshi Saito

IPC分类号： G11C7/00

CPC分类号： G11C29/34 ,  G11C16/04 ,  G11C2029/1204 ,  G11C2029/1802 ,  G11C2029/2602

摘要： There is disclosed a semiconductor integrated circuit device having first and second load circuits for write. At the time of an all bit-stress test, a high voltage for write is supplied from the first and second load circuits for write to the all bit lines. At the time of an even bit-stress test, the high voltage for write is supplied from the first load circuit for write to the even bit lines and a lower potential than the high voltage for write is supplied from the second load circuit for write to the odd bit lines. At the time of an odd bit-stress test, the lower potential is supplied from the first load circuit for write to the even bit lines and the high voltage for write is supplied from the second load circuit for write to the odd bit lines.

摘要翻译： 公开了一种具有用于写入的第一和第二负载电路的半导体集成电路器件。 在所有位应力测试时，从第一和第二负载电路提供用于写入的高电压用于写入所有位线。 在进行偶数位应力测试时，写入的高电压从第一负载电路提供给偶数位线，并且比写入的高电压低的电位从第二负载电路提供给写入 奇数位线。 在奇数位应力测试时，较低的电位从第一负载电路提供给偶数位线，并且用于写入的高电压从第二负载电路提供给奇数位线。

公开(公告)号：US07605434B2

公开(公告)日：2009-10-20

申请号：US11739381

申请日：2007-04-24

申请人： Tomohito Kawano

发明人： Tomohito Kawano

IPC分类号： G11C29/00

CPC分类号： G11C29/26 ,  G11C2029/2602

摘要： A semiconductor memory device of this invention includes a first bank, a second bank, and a bank decoder that selects a bank to be activated from the first and second banks. When testing operations of first memory cells and second memory cells, the bank decoder simultaneously selects the first and second banks, and first and second write load circuits simultaneously write data in memory cells in first and second blocks, respectively.

摘要翻译： 本发明的半导体存储器件包括第一存储体，第二存储体和存储体解码器，其从第一和第二存储体中选择要激活的存储体。 当第一存储器单元和第二存储单元的测试操作时，存储体解码器同时选择第一和第二存储体，并且第一和第二写入负载电路分别在第一和第二块中的存储单元中同时写入数据。

公开(公告)号：US20120072877A1

公开(公告)日：2012-03-22

申请号：US13229908

申请日：2011-09-12

申请人： Hideki TAKAHASHI ,  Tsuyoshi Etoh ,  Tomohito Kawano ,  Tatsuya Hiramatsu ,  Kiyoharu Murakami ,  Kouji Nakao

发明人： Hideki TAKAHASHI ,  Tsuyoshi Etoh ,  Tomohito Kawano ,  Tatsuya Hiramatsu ,  Kiyoharu Murakami ,  Kouji Nakao

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： According to one embodiment, a layout verification apparatus includes a design section, a layout creation section, a first verification section and a second verification section. One of the first and second verification sections includes a filter processing section which executes a filter processing of a verification target element to be verified by a mask data used to a manufacture of the semiconductor integrated circuit, and the verification target element to be verified needs an ion implantation. The filter processing section comprises a first logic section which executes an logical AND of the verification target element to be verified, a mask data necessary in order to form the verification target element to be verified, and a data inverted a mask data unnecessary in order to form the verification target element to be verified.

摘要翻译： 根据一个实施例，布局验证装置包括设计部分，布局创建部分，第一验证部分和第二验证部分。 第一和第二验证部分之一包括滤波处理部分，其执行将由用于制造半导体集成电路的掩模数据验证的验证目标元件的滤波处理，并且待验证的验证目标元件需要 离子注入。 滤波处理部分包括执行要验证的验证目标元件的逻辑与的第一逻辑部分，为了形成待验证的验证目标元件所必需的掩模数据，以及不需要的掩码数据的数据反转，以便 形成要验证的验证目标元素。

公开(公告)号：US20070266279A1

公开(公告)日：2007-11-15

申请号：US11739381

申请日：2007-04-24

申请人： Tomohito Kawano

发明人： Tomohito Kawano

IPC分类号： G11C29/00

CPC分类号： G11C29/26 ,  G11C2029/2602

摘要： A semiconductor memory device of this invention includes a first bank, a second bank, and a bank decoder that selects a bank to be activated from the first and second banks. When testing operations of first memory cells and second memory cells, the bank decoder simultaneously selects the first and second banks, and first and second write load circuits simultaneously write data in memory cells in first and second blocks, respectively.

摘要翻译： 本发明的半导体存储器件包括第一存储体，第二存储体和存储体解码器，其从第一和第二存储体中选择要激活的存储体。 当第一存储器单元和第二存储单元的测试操作时，存储体解码器同时选择第一和第二存储体，并且第一和第二写入负载电路分别在第一和第二块中的存储单元中同时写入数据。

公开(公告)号：US07755956B2

公开(公告)日：2010-07-13

申请号：US12129384

申请日：2008-05-29

申请人： Hitoshi Ohta ,  Tomohito Kawano

发明人： Hitoshi Ohta ,  Tomohito Kawano

IPC分类号： G11C11/00

CPC分类号： G11C29/4401 ,  G11C29/44 ,  G11C29/76

摘要： A non-volatile semiconductor memory includes a memory cell array. The memory cell array includes a plurality of banks, redundant blocks, and special blocks storing management data. Each bank includes a plurality of normal blocks, which include a plurality of electrically rewritable memory cells, the normal block being a minimum unit which is independently erased, and the redundant block configured to replace the normal block and being incapable of replacing the special block. A defective block automatic replacement sequence control circuit controls the replacement operation of the defective block FBLK with the redundant block RBLK in a defective block automatic replacement sequence.

摘要翻译： 非易失性半导体存储器包括存储单元阵列。 存储单元阵列包括多个存储体，冗余块和存储管理数据的特殊块。 每个存储体包括多个正常块，其包括多个电可重写存储单元，该正常块是被独立擦除的最小单位，并且冗余块被配置为替换正常块并且不能替换该特殊块。 故障块自动替换序列控制电路利用冗余块RBLK在缺陷块自动替换序列中控制缺陷块FBLK的替换操作。

公开(公告)号：US20090279357A1

公开(公告)日：2009-11-12

申请号：US12433173

申请日：2009-04-30

申请人： Hitoshi OHTA ,  Tomohito Kawano ,  Akira Umezawa

发明人： Hitoshi OHTA ,  Tomohito Kawano ,  Akira Umezawa

IPC分类号： G11C16/04 ,  G11C29/00 ,  G11C5/14

CPC分类号： G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C29/12 ,  G11C2029/1202 ,  G11C2029/1802

摘要： A nonvolatile semiconductor storage device includes a memory cell array including a plurality of memory cells arranged at intersection positions of word lines and bit lines in a matrix form, and a row decoder including a row sub-decoder to which a lower address for selecting a word line is input, wherein one unit of the row sub-decoder for selecting one word line is constituted of a first transistor of a first conduction type, and a second transistor of a second conduction type, and a gate electrode of each of the first and second transistors is arranged in a direction in which the bit lines are arranged.

摘要翻译： 非易失性半导体存储装置包括存储单元阵列，其包括以矩阵形式布置在字线和位线的交叉位置处的多个存储单元，以及行解码器，包括行子解码器，用于选择字的较低地址 行，其中用于选择一个字线的行子解码器的一个单元由第一导电类型的第一晶体管和第二导电类型的第二晶体管和第一和第二导体的第二晶体管构成， 第二晶体管沿排列位线的方向排列。

公开(公告)号：US20080298126A1

公开(公告)日：2008-12-04

申请号：US12129384

申请日：2008-05-29

申请人： Hitoshi OHTA ,  Tomohito Kawano

发明人： Hitoshi OHTA ,  Tomohito Kawano

IPC分类号： G11C16/06

CPC分类号： G11C29/4401 ,  G11C29/44 ,  G11C29/76

摘要： A non-volatile semiconductor memory includes a memory cell array. The memory cell array includes a plurality of banks, redundant blocks, and special blocks storing management data. Each bank includes a plurality of normal blocks, which include a plurality of electrically rewritable memory cells, the normal block being a minimum unit which is independently erased, and the redundant block configured to replace the normal block and being incapable of replacing the special block. A defective block automatic replacement sequence control circuit controls the replacement operation of the defective block FBLK with the redundant block RBLK in a defective block automatic replacement sequence.

摘要翻译： 非易失性半导体存储器包括存储单元阵列。 存储单元阵列包括多个存储体，冗余块和存储管理数据的特殊块。 每个存储体包括多个正常块，其包括多个电可重写存储单元，该正常块是被独立擦除的最小单位，并且冗余块被配置为替换正常块并且不能替换该特殊块。 故障块自动替换序列控制电路利用冗余块RBLK在缺陷块自动替换序列中控制缺陷块FBLK的替换操作。

公开(公告)号：US20070183233A1

公开(公告)日：2007-08-09

申请号：US11669420

申请日：2007-01-31

申请人： Tomohito Kawano ,  Hidetoshi Saito

发明人： Tomohito Kawano ,  Hidetoshi Saito

IPC分类号： G11C29/00 ,  G11C16/06 ,  G11C11/34 ,  G11C7/00

CPC分类号： G11C29/34 ,  G11C16/04 ,  G11C2029/1204 ,  G11C2029/1802 ,  G11C2029/2602

摘要： There is disclosed a semiconductor integrated circuit device having first and second load circuits for write. At the time of an all bit-stress test, a high voltage for write is supplied from the first and second load circuits for write to the all bit lines. At the time of an even bit-stress test, the high voltage for write is supplied from the first load circuit for write to the even bit lines and a lower potential than the high voltage for write is supplied from the second load circuit for write to the odd bit lines. At the time of an odd bit-stress test, the lower potential is supplied from the first load circuit for write to the even bit lines and the high voltage for write is supplied from the second load circuit for write to the odd bit lines.

摘要翻译： 公开了一种具有用于写入的第一和第二负载电路的半导体集成电路器件。 在所有位应力测试时，从第一和第二负载电路提供用于写入的高电压用于写入所有位线。 在进行偶数位应力测试时，写入的高电压从第一负载电路提供给偶数位线，并且比写入的高电压低的电位从第二负载电路提供给写入 奇数位线。 在奇数位应力测试时，较低的电位从第一负载电路提供给偶数位线，并且用于写入的高电压从第二负载电路提供给奇数位线。

公开(公告)号：US20050184771A1

公开(公告)日：2005-08-25

申请号：US11017750

申请日：2004-12-22

申请人： Kiyotaka Uchigane ,  Tomohito Kawano

发明人： Kiyotaka Uchigane ,  Tomohito Kawano

IPC分类号： G01R31/28 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  H03K17/22 ,  H03L7/00

CPC分类号： H03K17/223

摘要： A semiconductor device is disclosed, which comprises a voltage dividing resistor circuit including a plurality of resistor elements connected in series between a power supply node and a ground node, a voltage detecting PMOS transistor having a gate connected to an output node of the voltage dividing resistor circuit and a source connected to the power supply node, a resistor element connected between a drain of the voltage detecting PMOS transistor and a ground node, a CMOS inverter circuit supplied with a power supply voltage through the power supply node, having an input terminal connected to a drain of the voltage detecting PMOS transistor and an output terminal for outputting a power-on detection signal, and a monitoring pad which monitors a potential of the output node of the voltage dividing resistor circuit from exterior of a semiconductor chip.

摘要翻译： 公开了一种半导体器件，其包括分压电阻器电路，其包括串联连接在电源节点和接地节点之间的多个电阻元件，电压检测PMOS晶体管，其栅极连接到分压电阻器的输出节点 电路和连接到电源节点的源极，连接在电压检测PMOS晶体管的漏极和接地节点之间的电阻元件，经由电源节点提供有电源电压的CMOS反相器电路，具有连接的输入端子 到电压检测PMOS晶体管的漏极和用于输出上电检测信号的输出端子，以及监控焊盘，其从半导体芯片的外部监视分压电阻器电路的输出节点的电位。