公开(公告)号：US5581103A

公开(公告)日：1996-12-03

申请号：US271146

申请日：1994-07-06

申请人： Shigeto Mizukami

发明人： Shigeto Mizukami

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/78 ,  H02H7/20

CPC分类号： H01L27/0266

摘要： A semiconductor integrated circuit device, comprises: an n.sup.+ -type buried layer 12 formed on a surface of a p-type semiconductor substrate 11; an n-type semiconductor layer 71 formed on the n.sup.+ -type buried layer 12; a first p type well 16 formed in the semiconductor layer 71; a second p-type well 18 formed in the semiconductor layer 71 and electrically isolated from the first p-type well 16; an input-protecting N-type MOS transistor 102 formed in the first p-type well 16 and having a drain 22 grounded, a source 25 connected to an input terminal 101 to which an external signal is input, and a gate 23 grounded; and an n.sup.+ -type impurity region 27 grounded and formed in the second p-type well 18. Whenever a negative surge voltage is applied to the input terminal 101, a current path is formed from the ground V.sub.SS to the input terminal 101, by way of the impurity region 27 formed in the second p-type well 18, the n.sup.+ -type buried layer 12, and the source 25 formed in the first p-type well 16, in addition to the current path through the input-protecting N-type MOS transistor 102 formed in the first p-type well 16, thus improving the input-protection characteristics of the circuits formed in the same semiconductor substrate against a surge voltage applied to the input terminal 101.

摘要翻译： 一种半导体集成电路器件，包括：形成在p型半导体衬底11的表面上的n +型掩埋层12; 形成在n +型掩埋层12上的n型半导体层71; 形成在半导体层71中的第一p型阱16; 形成在半导体层71中并与第一p型阱16电隔离的第二p型阱18; 形成在第一p型阱16中并具有接地的漏极22的输入保护N型MOS晶体管102，与输入外部信号的输入端子101连接的源极25和接地的栅极23; 以及在第二p型阱18中接地形成的n +型杂质区27.无论何时向输入端101施加负浪涌电压，通过接地VSS至输入端101形成电流路径 形成在第二p型阱18中的杂质区域27，n +型掩埋层12和形成在第一p型阱16中的源极25，除了通过输入保护N- 形成在第一p型阱16中的MOS晶体管102，从而提高了形成在同一半导体衬底中的电路的输入保护特性，抵抗施加到输入端101的浪涌电压。

公开(公告)号：US5487044A

公开(公告)日：1996-01-23

申请号：US372906

申请日：1995-01-17

申请人： Takayuki Kawaguchi ,  Shigeto Mizukami ,  Yasumitsu Nozawa ,  Kouji Nakao

发明人： Takayuki Kawaguchi ,  Shigeto Mizukami ,  Yasumitsu Nozawa ,  Kouji Nakao

IPC分类号： G11C11/41 ,  G11C7/12 ,  H01L27/10 ,  G11C7/00

CPC分类号： G11C7/12

摘要： A semiconductor memory device having memory cells arranged in a matrix, each of the memory cells having input/output terminals, word lines for selecting the memory cells, pairs of bit lines connected to the input/output terminals, bit line pulling-up means for pulling up the potential of the bit lines, bit line loading means connected to another pair of bit lines and bit line equalizing means provided for the bit lines for equalizing the potential of the bit lines by allowing conduction between the bit lines before data is read from a selected memory cell.

摘要翻译： 一种具有以矩阵形式布置的存储单元的半导体存储器件，每个存储器单元具有输入/输出端子，用于选择存储单元的字线，连接到输入/输出端子的位线对，位线提升装置， 提高位线的电位，连接到另一对位线的位线加载装置和为位线提供的位线均衡装置，用于通过在读取数据之前允许位线之间的导通来均衡位线的电位 选择的存储单元。

公开(公告)号：US5459423A

公开(公告)日：1995-10-17

申请号：US77737

申请日：1993-06-18

申请人： Yasumitsu Nozawa ,  Shigeto Mizukami ,  Makoto Segawa

发明人： Yasumitsu Nozawa ,  Shigeto Mizukami ,  Makoto Segawa

IPC分类号： G11C11/41 ,  G05F1/46 ,  G11C7/22 ,  G11C11/407 ,  G11C11/413 ,  H01L27/10 ,  H03K5/13 ,  H04B1/40 ,  H03K5/153 ,  H03K5/159

CPC分类号： G11C7/22 ,  G05F1/466 ,  H03K5/133

摘要： A delay circuit is interposed between first and second circuit systems both driven by a first supply voltage. The delay circuit delays a signal applied by the first circuit system, and then transmits the delayed signal to the second circuit system. In particular, a constant voltage supply circuit generates a second supply voltage (constant voltage) on the basis of the first supply voltage, and supplies the constant voltage to this delay circuit, so that a stable constant delay time can be obtained by the delay circuit without being subjected to the influence of fluctuations of the first supply voltage. All the circuit elements are formed on the same semiconductor substrate. Further, it is preferable to construct the constant voltage supply circuit in such a way that the output voltage thereof is programmable.

摘要翻译： 延迟电路插在由第一电源电压驱动的第一和第二电路系统之间。 延迟电路延迟由第一电路系统施加的信号，然后将延迟的信号发送到第二电路系统。 特别地，恒压电源电路基于第一电源电压产生第二电源电压（恒定电压），并将恒定电压提供给该延迟电路，从而可以通过延迟电路获得稳定的恒定延迟时间 而不受第一电源电压波动的影响。 所有电路元件形成在相同的半导体衬底上。 此外，优选构造恒定电压供给电路，使得其输出电压是可编程的。

公开(公告)号：US5455795A

公开(公告)日：1995-10-03

申请号：US341418

申请日：1994-11-17

申请人： Kouji Nakao ,  Shigeto Mizukami

发明人： Kouji Nakao ,  Shigeto Mizukami

IPC分类号： G11C17/18 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  G11C11/41 ,  G11C16/02 ,  G11C17/00 ,  G11C13/00

CPC分类号： G11C7/1033

摘要： A semiconductor memory device comprises a page access mode, a plurality of sense amplifiers for detecting data read from a plurality of memory cells selected based on first address inputs A2 to An, a plurality of latch circuits for latching data from the plurality of sense amplifiers, a reading circuit for reading latch data based on second address inputs A0 and A1 corresponding to the plurality of latch circuits, and a control circuit for controlling the sense amplifier to be activated when only the first address input or both first and second address inputs are changed, and to be inactivated when only the second address input is changed.

摘要翻译： 半导体存储器件包括页访问模式，用于检测从基于第一地址输入A2至An所选择的多个存储单元读取的数据的多个读出放大器，用于锁存来自多个读出放大器的数据的多个锁存电路， 读取电路，用于基于与多个锁存电路相对应的第二地址输入A0和A1读取锁存数据;以及控制电路，用于当只有第一地址输入或第一和第二地址输入都被改变时控制读出放大器被激活 ，并且仅在第二地址输入改变时被禁用。

公开(公告)号：US4939691A

公开(公告)日：1990-07-03

申请号：US260427

申请日：1988-10-20

申请人： Shigeto Mizukami ,  Makoto Segawa

发明人： Shigeto Mizukami ,  Makoto Segawa

IPC分类号： G11C11/417 ,  G11C11/409 ,  G11C11/419

CPC分类号： G11C11/419

摘要： In a static random access memory, when data is written into said plurality of memory cells, a write enable signal is set at a low level, and after the data write is completed, the write enable signal is set at a high level. In response to a level change of the write enable signal from a low level to a high level, a pulse generator generates a pulse signal in "1" level and with a given pulse width. In response to this pulse signal, a first MOS transistor is turned on to short paired bit lines. This pulse signal turns on second and third MOS transistors. Then, the potentials on the paired bit lines are pulled up to a power source potential. As a result, of the two bit lines, the bit line which has been set at a low potential immediately after data is written, is charged. A pulse extension/inverting circuit extends the pulse width of the pulse signal generated by a pulse generator by a given time period, and inverts a logical state of the pulse signal. During a period that the first MOS transistor shorts the bit lines to place the equal potentials on the bit lines, the pulse signal .phi.WRD output from the pulse extension/inverting circuit is kept in "0" level. During this period, therefore, the output data of two AND gates is "0" level irrespective of the sensed data from a read circuit and the supply of the sensed data from the read circuit to a data output circuit is stopped.

摘要翻译： 在静态随机存取存储器中，当将数据写入所述多个存储单元时，写入使能信号被设置为低电平，并且在数据写入完成之后，写使能信号被设置为高电平。 响应于写使能信号从低电平到高电平的电平变化，脉冲发生器产生具有“1”电平和给定脉冲宽度的脉冲信号。 响应于该脉冲信号，第一MOS晶体管导通短对成对的位线。 该脉冲信号接通第二和第三MOS晶体管。 然后，成对位线上的电位被拉到电源电位。 结果，在两个位线之间，在写入数据之后立即被设置为低电位的位线被充电。 脉冲扩展/反相电路将由脉冲发生器产生的脉冲信号的脉冲宽度延长给定的时间周期，并且使脉冲信号的逻辑状态反相。 在第一MOS晶体管使位线短路以将相等电位置于位线的期间内，从脉冲扩展/反相电路输出的脉冲信号phi WRD保持为“0”电平。 因此，在此期间，与读取电路的感测数据无关，两个与门的输出数据为“0”电平，并且停止从读取电路向数据输出电路的感测数据的供给。

公开(公告)号：US4760560A

公开(公告)日：1988-07-26

申请号：US900517

申请日：1986-08-26

申请人： Shoji Ariizumi ,  Makoto Segawa ,  Shigeto Mizukami

发明人： Shoji Ariizumi ,  Makoto Segawa ,  Shigeto Mizukami

IPC分类号： G05F3/20 ,  G11C5/14 ,  H01L27/02 ,  H01L27/105 ,  G11C7/00 ,  G11C11/34 ,  H01L27/10 ,  H01L27/15

CPC分类号： G05F3/205 ,  G11C5/146 ,  H01L27/0218 ,  H01L27/105

摘要： A random access memory comprises a semiconductor body of one conductivity type, at least one first well region of an opposite conductivity type formed in the surface area of the semiconductor body, and a memory cell array having a plurality of memory cells formed in the first well region. A peripheral circuit for driving the memory cell array is formed in at least one second well region of the opposite conductivity type formed separately from the first well region in the surface area of the semiconductor body. The second well region is set at a bias level deeper than the first well region.

摘要翻译： 随机存取存储器包括一个导电类型的半导体本体，形成在该半导体本体的表面区域中的至少一个相反导电类型的第一阱区，以及一个存储单元阵列，具有形成在第一阱中的多个存储单元 地区。 用于驱动存储单元阵列的外围电路形成在与半导体本体的表面区域中的第一阱区分开形成的相反导电类型的至少一个第二阱区域中。 第二阱区被设置在比第一阱区更深的偏置电平。