公开(公告)号：US09176522B1

公开(公告)日：2015-11-03

申请号：US14267933

申请日：2014-05-02

申请人： Amit Kumar Dey ,  Himanshu Mangal ,  Kulbhushan Misri ,  Amit Roy ,  Vijay Tayal ,  Chetan Verma

发明人： Amit Kumar Dey ,  Himanshu Mangal ,  Kulbhushan Misri ,  Amit Roy ,  Vijay Tayal ,  Chetan Verma

IPC分类号： G06F1/04 ,  H03K3/00 ,  H03K19/20

CPC分类号： G06F1/04 ,  H03K19/096 ,  H03K19/20

摘要： A clock signal generator provides a gated clock signal GCLK to trigger operation of dual-edge triggered circuits. A first detector generates, while a clock gating signal /EN is asserted, a first detector output signal that is asserted or de-asserted as a function of disjunction or conjunction respectively of the values that an input clock signal CLK and the gated clock signal GCLK had when the clock gating signal /EN transitioned. A second detector generates, while the clock gating signal /EN is de-asserted, as the value of the gated clock signal GCLK, the value CLK or its complement /CLK as a function of the first detector output signal. When the clock gating signal /EN is asserted, the second detector maintains the value that the gated clock signal GCLK had when the clock gating signal /EN transitioned from de-asserted to asserted.

摘要翻译： 时钟信号发生器提供门控时钟信号GCLK以触发双边缘触发电路的操作。 当时钟门控信号/ EN被断言时，第一检测器产生一个第一检测器输出信号，该第一检测器输出信号被断言或取消断言作为分离或分别与输入时钟信号CLK和门控时钟信号GCLK 当时钟门控信号/ EN转换。 当门控时钟信号/ EN被取消置位时，第二个检测器产生门控时钟信号GCLK的值，作为第一检测器输出信号的函数的值CLK或其补码/ CLK。 当时钟选通信号/ EN被断言时，第二个检测器保持门控时钟信号GCLK当时钟门控信号/ EN从解除断言转变为有效时所具有的值。

公开(公告)号：US20070018864A1

公开(公告)日：2007-01-25

申请号：US11490441

申请日：2006-07-20

申请人： Qadeer Khan ,  Sanjay Wadhwa ,  Divya Tripathi ,  Siddhartha Gk ,  Kulbhushan Misri

发明人： Qadeer Khan ,  Sanjay Wadhwa ,  Divya Tripathi ,  Siddhartha Gk ,  Kulbhushan Misri

IPC分类号： H03M1/06

CPC分类号： H03K19/00384

摘要： A compensation circuit and a method that compensates for process, voltage and temperature (PVT) variations in an integrated circuit that includes functional modules. The compensation circuit includes a signal generator, a first code generator, a second code generator, and a mapping module. The signal generator generates a first signal and a second signal depending on aligned process corner, voltage and temperature variations and skewed process corner variations respectively. The first code generator receives the first signal, and generates a first calibration code. The second code generator receives the second signal, and generates a second calibration code. The mapping module provides the first and second calibration codes for compensating for the aligned process corner, voltage and temperature variations and the skewed process corner variations associated with the functional modules respectively.

摘要翻译： 补偿电路和补偿包含功能模块的集成电路中的工艺，电压和温度（PVT）变化的方法。 补偿电路包括信号发生器，第一代码发生器，第二代码生成器和映射模块。 信号发生器分别根据对齐的过程角，电压和温度变化以及偏斜过程角变化产生第一信号和第二信号。 第一代码生成器接收第一信号，并产生第一校准码。 第二代码生成器接收第二信号，并产生第二校准码。 映射模块提供第一和第二校准码，用于分别补偿与功能模块相关联的对准过程角，电压和温度变化以及偏斜的过程角变化。

公开(公告)号：US20070018713A1

公开(公告)日：2007-01-25

申请号：US11490440

申请日：2006-07-20

申请人： Divya Tripathi ,  Siddhartha Gk ,  Qadeer Khan ,  Kulbhushan Misri ,  Sanjay Wadhwa

发明人： Divya Tripathi ,  Siddhartha Gk ,  Qadeer Khan ,  Kulbhushan Misri ,  Sanjay Wadhwa

IPC分类号： H01L35/00

CPC分类号： H03K19/00384

摘要： A compensation circuit and a method for detecting and compensating for process, voltage, and temperature (PVT) variations in an integrated circuit. The integrated circuit includes plural logic modules that include PMOS transistors and NMOS transistors. The compensation circuit includes first and second functional modules, which generate first and second calibration signals. The first and the second calibration signals are used to compensate for the PVT variations in PMOS and NMOS transistors.

摘要翻译： 一种用于检测和补偿集成电路中的过程，电压和温度（PVT）变化的补偿电路和方法。 集成电路包括包括PMOS晶体管和NMOS晶体管的多个逻辑模块。 补偿电路包括产生第一和第二校准信号的第一和第二功能模块。 第一和第二校准信号用于补偿PMOS和NMOS晶体管中的PVT变化。

公开(公告)号：US20060012409A1

公开(公告)日：2006-01-19

申请号：US10892420

申请日：2004-07-15

申请人： Sanjay Wadhwa ,  Kulbhushan Misri ,  Deeya Muhury ,  Murugesan Raman

发明人： Sanjay Wadhwa ,  Kulbhushan Misri ,  Deeya Muhury ,  Murugesan Raman

IPC分类号： H03L7/00

CPC分类号： H03K17/223

摘要： A power on reset (POR) circuit for providing a reset pulse signal to a chip when power supply voltage, VDD, ramps up so that the chip always starts in a known state. The POR circuit generates the reset pulse as soon as VDD exceeds an assertion voltage. The assertion voltage is independent of the ramp rate of VDD. The POR circuit is shut off as soon as the reset signal is generated, thereby drawing zero steady state current from VDD. The re-arm time for the POR circuit is very small. The POR circuit does not reset the chip when there is a dynamic change in VDD.

摘要翻译： 上电复位（POR）电路，用于在电源电压VDD上升时向芯片提供复位脉冲信号，以使芯片始终处于已知状态。 一旦VDD超过断言电压，POR电路就会产生复位脉冲。 断言电压与VDD的斜坡率无关。 一旦产生复位信号，POR电路就会关闭，从而从VDD引起零稳态电流。 POR电路的重新布置时间非常小。 当VDD发生动态变化时，POR电路不会复位芯片。

公开(公告)号：US09292651B2

公开(公告)日：2016-03-22

申请号：US14195827

申请日：2014-03-03

申请人： Chetan Verma ,  Amit Kumar Dey ,  Ashis Maitra ,  Kulbhushan Misri ,  Amit Roy ,  Harkaran Singh ,  Vijay Tayal

发明人： Chetan Verma ,  Amit Kumar Dey ,  Ashis Maitra ,  Kulbhushan Misri ,  Amit Roy ,  Harkaran Singh ,  Vijay Tayal

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5072 ,  G06F2217/84

摘要： A method of physical design of an IC using an EDA tool includes identifying elements of the IC design that have excess positive timing slack. The excess timing slack elements are placed in a separate partition and then parameters of the characteristics of the excess timing slack elements are modified to reduce their excess timing slack, such as reducing the voltage supplied to the separate partition, thereby lowering power consumption of the IC design.

摘要翻译： 使用EDA工具的IC的物理设计方法包括识别具有过多正时序松弛的IC设计的元件。 过多的定时松弛元件被放置在单独的分区中，然后修改多余的定时松弛元件的特性的参数以减少它们的超时间松弛，例如降低提供给单独隔板的电压，从而降低IC的功耗 设计。

公开(公告)号：US07187197B2

公开(公告)日：2007-03-06

申请号：US11098108

申请日：2005-04-04

申请人： Divya Tripathi ,  Qadeer A. Khan ,  Kulbhushan Misri

发明人： Divya Tripathi ,  Qadeer A. Khan ,  Kulbhushan Misri

IPC分类号： H03K5/12 ,  H03K19/094 ,  H03K3/00

CPC分类号： G06F13/4072 ,  H03K19/00361

摘要： A transmission line driver with slew rate control includes high and low side ramp generators for generating charge and discharge ramp signals, respectively, which are input to respective comparators and a pair of source follower transistors. A pair of additional transistors is connected to the pair of source follower transistors and a pair of staggered drivers is connected to the pair of additional transistors.

摘要翻译： 具有压摆率控制的传输线驱动器包括分别产生充放电斜坡信号的高低侧斜坡发生器，其分别输入到各个比较器和一对源极跟随器晶体管。 一对附加晶体管连接到一对源极跟随器晶体管，并且一对交错驱动器连接到该对附加晶体管。

公开(公告)号：US20070018712A1

公开(公告)日：2007-01-25

申请号：US11490439

申请日：2006-07-20

申请人： Siddhartha GK ,  Qadeer Khan ,  Divya Tripathi ,  Sanjay Wadhwa ,  Kulbhushan Misri

发明人： Siddhartha GK ,  Qadeer Khan ,  Divya Tripathi ,  Sanjay Wadhwa ,  Kulbhushan Misri

IPC分类号： H01L35/00

CPC分类号： H03K19/00369

摘要： A compensation circuit and a method for compensating for process, voltage and temperature (PVT) variations in an integrated circuit (IC). The IC includes several functional modules, each of which includes a set of functional units, and generates an output signal in response to an input signal. The compensation circuit includes a code generator and a logic module. The code generator generates a digital code for each functional unit. The digital codes are based on phase differences between the input signal and the output signal. The logic module generates calibration codes based on the digital codes. The calibration codes compensate for the PVT variations in the corresponding functional units.

摘要翻译： 补偿电路和补偿集成电路（IC）中的工艺，电压和温度（PVT）变化的方法。 IC包括几个功能模块，每个功能模块包括一组功能单元，并且响应于输入信号产生输出信号。 补偿电路包括代码生成器和逻辑模块。 代码生成器为每个功能单元生成数字代码。 数字码基于输入信号和输出信号之间的相位差。 逻辑模块基于数字代码生成校准代码。 校准代码补偿相应功能单元中的PVT变化。

公开(公告)号：US07084698B2

公开(公告)日：2006-08-01

申请号：US10964793

申请日：2004-10-14

申请人： Qadeer A. Khan ,  Sanjay K. Wadhwa ,  Kulbhushan Misri

发明人： Qadeer A. Khan ,  Sanjay K. Wadhwa ,  Kulbhushan Misri

IPC分类号： G05F1/10

CPC分类号： G05F3/30

摘要： A band-gap reference circuit for generation of voltages and currents independent of process, voltage, and temperature includes three inversely proportional to absolute temperature (IPTAT) current generators. The IPTAT current generators generate three currents that are added to generate a current independent of the absolute temperature. The generated current is passed through a switched capacitor resistor to generate the band-gap reference voltage across the switched capacitor resistor.

摘要翻译： 用于产生独立于过程，电压和温度的电压和电流的带隙基准电路包括与绝对温度（IPTAT）电流发生器成反比的三个。 IPTAT电流发生器产生三个电流，其被添加以产生独立于绝对温度的电流。 所产生的电流通过开关电容电阻器，以产生开关电容电阻两端的带隙基准电压。

公开(公告)号：US20150248519A1

公开(公告)日：2015-09-03

申请号：US14195827

申请日：2014-03-03

申请人： Chetan Verma ,  Amit Kumar Dey ,  Ashis Maitra ,  Kulbhushan Misri ,  Amit Roy ,  Harkaran Singh ,  Vijay Tayal

发明人： Chetan Verma ,  Amit Kumar Dey ,  Ashis Maitra ,  Kulbhushan Misri ,  Amit Roy ,  Harkaran Singh ,  Vijay Tayal

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5072 ,  G06F2217/84

摘要： A method of physical design of an IC using an EDA tool includes identifying elements of the IC design that have excess positive timing slack. The excess timing slack elements are placed in a separate partition and then parameters of the characteristics of the excess timing slack elements are modified to reduce their excess timing slack, such as reducing the voltage supplied to the separate partition, thereby lowering power consumption of the IC design.

摘要翻译： 使用EDA工具的IC的物理设计方法包括识别具有过多正时序松弛的IC设计的元件。 过多的定时松弛元件被放置在单独的分区中，然后修改多余的定时松弛元件的特性的参数以减少它们的过多的定时松弛，例如降低提供给单独隔板的电压，从而降低IC的功耗 设计。

公开(公告)号：US07102410B2

公开(公告)日：2006-09-05

申请号：US10865363

申请日：2004-06-10

申请人： Qadeer A. Khan ,  Divya Tripathi ,  Kulbhushan Misri

发明人： Qadeer A. Khan ,  Divya Tripathi ,  Kulbhushan Misri

IPC分类号： H03L5/00

CPC分类号： H03F3/45183

摘要： A circuit for converting an input signal at a first voltage level to an output signal at a second voltage level uses only thin oxide transistors. The circuit includes a first unit operating at a first power supply voltage and receiving the input signal, a second unit operating at a second power supply voltage, and a third unit coupling the first unit to the second unit. The third unit enables generation of the output signal. Use of an extra fabrication mask for thick oxide transistors is avoided by using only thin oxide transistors.

摘要翻译： 用于将第一电压电平的输入信号转换为第二电压电平的输出信号的电路仅使用薄氧化物晶体管。 电路包括以第一电源电压工作并接收输入信号的第一单元，以第二电源电压工作的第二单元，以及将第一单元耦合到第二单元的第三单元。 第三单元能够产生输出信号。 通过仅使用薄氧化物晶体管避免了对厚氧化物晶体管使用额外的制造掩模。