公开(公告)号：US10814199B1

公开(公告)日：2020-10-27

申请号：US16546443

申请日：2019-08-21

Applicant: Kun-Cheng Wu ,  Fan Chia

Inventor： Kun-Cheng Wu ,  Fan Chia

IPC: A63B69/00 ,  A63B63/08 ,  A63B71/06 ,  A63B63/00

Abstract: A basketball shooting training includes a stand, a rotatable hoop module, a blocking module, and a guide module. The stand includes a horizontal segment and a vertical segment. The rotatable hoop module includes a frame and a backboard. The blocking module includes two columns, a collection member, an obstruction unit, and two fixed pulley sets. The guide module includes a conducting device mounted on the horizontal segment of the stand, and the supply portion extends outward from the stand. The mounting of the stand is fixed on a bottom of the conducting device, and the rotatable hoop module further includes a support post on which the backboard is disposed. A movable seat is connected on a bottom of the support post, the movable seat is disposed on and rotates along the mounting, and the conducting device has an arcuate track on which the support post slides.

公开(公告)号：US07596772B2

公开(公告)日：2009-09-29

申请号：US11608248

申请日：2006-12-08

Applicant: Hanping Chen ,  Chih-Yang Peng ,  Alvin Hsin-Hung Chen ,  Jia-Jio Huang ,  Jim Jyh-Herng Wang ,  Kun-Cheng Wu

Inventor： Hanping Chen ,  Chih-Yang Peng ,  Alvin Hsin-Hung Chen ,  Jia-Jio Huang ,  Jim Jyh-Herng Wang ,  Kun-Cheng Wu

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F17/5036

Abstract: A fast methodology and system to characterize setup/hold time for analog IPs are provided. Partial circuits of clock and data paths are simulated instead of the simulation of entire IPs. The partial circuits include all those paths of clock pin and data input pins before reaching first level DFF. This methodology includes multi-path searching of hierarchical SPICE netlist for the path of clock pin and data pins, so as to reduce the circuit subset, merge the paths of clock pin and the data pins, and characterize the setup/hold time for the analog IP. The paths of data pins and clock pin before DFF are used for setup/hold time characterization.

Abstract translation: 提供了一种用于表征模拟IP的设置/保持时间的快速方法和系统。 模拟时钟和数据路径的部分电路，而不是整个IP的仿真。 部分电路包括达到第一级DFF之前的时钟引脚和数据输入引脚的所有路径。 该方法包括多路径搜索时钟引脚和数据引脚路径的分层SPICE网表，以减少电路子集，合并时钟引脚和数据引脚的路径，并表征模拟的建立/保持时间 IP。 DFF之前的数据引脚和时钟引脚的路径用于建立/保持时间表征。

公开(公告)号：US07290231B2

公开(公告)日：2007-10-30

申请号：US10710420

申请日：2004-07-09

Applicant: Kun-Cheng Wu ,  Chien-Ming Huang

Inventor： Kun-Cheng Wu ,  Chien-Ming Huang

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F17/5045

Abstract: A method for reducing standard delay format (SDF) file size is disclosed. The state-dependent descriptions in cell descriptions of the SDF file, which are not intended to be used, are removed by referring to a design description of an integrated circuit design. Therefore, the SDF file size is reduced and the simulation result generated by a simulator is not affected with the reduced SDF file.

Abstract translation: 公开了一种降低标准延迟格式（SDF）文件大小的方法。 通过参考集成电路设计的设计描述来去除不想使用的SDF文件的单元描述中的状态相关描述。 因此，减少了SDF文件大小，并且模拟器生成的仿真结果不受缩小的SDF文件的影响。

公开(公告)号：US20070214438A1

公开(公告)日：2007-09-13

申请号：US11308154

申请日：2006-03-09

Applicant: Peter H. Chen Hanping Chen ,  Jyh-Herng Wang ,  Chih-Yang Peng ,  Han-Chi Liu ,  Hsin-Hung Chen ,  Kun-Cheng Wu

Inventor： Peter H. Chen Hanping Chen ,  Jyh-Herng Wang ,  Chih-Yang Peng ,  Han-Chi Liu ,  Hsin-Hung Chen ,  Kun-Cheng Wu

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: A method for static power characterization of an analog integrated circuit includes detecting whether each of a plurality of input pins is electrically connected to a specific circuit; selecting a plurality of test benches of the static power characterization according to a number of the input pins electrically connected to the specific circuit; and processing the plurality of selected test benches of the static power characterization.

Abstract translation: 一种用于模拟集成电路的静态功率表征的方法包括检测多个输入引脚中的每一个是否电连接到特定电路; 根据电连接到特定电路的输入引脚的数量来选择静态功率表征的多个测试台; 以及处理静态功率表征的多个选定测试台。

公开(公告)号：US06382846B1

公开(公告)日：2002-05-07

申请号：US09004870

申请日：1998-01-09

Applicant: George Shiang-Jyh Lai ,  Ruey-Liang Ma ,  Dze-chaung Wang ,  Shi-Sheng Shang ,  Kun-Cheng Wu

Inventor： George Shiang-Jyh Lai ,  Ruey-Liang Ma ,  Dze-chaung Wang ,  Shi-Sheng Shang ,  Kun-Cheng Wu

IPC: G06F945

CPC classification number: G06F9/44521

Abstract: A processor is provided with a decoder, a memory connected to the decoder and an execution stage connected to the decoder. The decoder receives each instruction. Each time the decoder receives an instruction, if the instruction contains a symbolic reference, the decoder determines whether or not the symbolic reference has been resolved into a numeric operand. If the symbolic reference has been resolved into a numeric operand, the memory retrieves, from a numeric reference table, a numeric operand to which the symbolic reference has been resolved. The execution stage then executes the instruction on the retrieved numeric operand in place of the symbolic reference. If the symbolic reference has not been resolved into a numeric operand, then the execution stage searches a data object, which relates each symbolic reference to a memory slot in which a corresponding numeric operand is stored, for a numeric reference relating the symbolic reference to a corresponding numeric operand. The memory then retrieves the numeric operand, that corresponds to the unresolved symbolic reference, from the memory slot indicated by the numeric reference of the data object. The memory stores the retrieved numeric operand in the numeric reference table maintained therein. The execution stage executes the instruction on the retrieved numeric operand in place of the symbolic reference of the instruction and indicates to the decoder that the symbolic reference is resolved. “Resolved indications,” which each indicates whether or not a specific, respective symbolic reference is resolved, can be stored in a numeric reference buffer and accessed using the instruction fetch address as an index. The numeric reference table can also be stored in the numeric reference buffer and accessed (indexed) the same way.

Abstract translation: 处理器设置有解码器，连接到解码器的存储器和连接到解码器的执行级。 解码器接收每条指令。 每当解码器接收到指令时，如果指令包含符号参考，则解码器确定符号引用是否已被解析为数字操作数。 如果符号引用已被解析为数字操作数，则内存将从数字参考表中检索已解析符号引用的数字操作数。 执行阶段然后执行关于检索的数字操作数的指令代替符号引用。 如果符号引用尚未解析成数字操作数，则执行阶段搜索数据对象，该数据对象将每个符号引用与其中存储对应的数字操作数的存储器槽相关联，用于将符号引用与数字对象相关联 对应的数字操作数。 然后，存储器从数据对象的数字参考指示的存储槽中检索对应于未解析的符号引用的数字操作数。 存储器将检索的数字操作数存储在其中维护的数字参考表中。 执行级代替检索的数字操作数的指令代替指令的符号引用，并向解码器指示符号引用被解析。 “解决的指示”，其各自指示特定的相应符号引用是否被解析，可以存储在数字参考缓冲器中并且使用指令获取地址作为索引进行访问。 数字参考表也可以存储在数字参考缓冲区中，以相同的方式访问（索引）。

公开(公告)号：US06199491B1

公开(公告)日：2001-03-13

申请号：US09569785

申请日：2000-05-12

Applicant: Kun-Cheng Wu

Inventor： Kun-Cheng Wu

IPC: F23J1500

CPC classification number: F23G5/165 ,  F23G5/004 ,  F23G5/16 ,  F23G2203/80 ,  F23G2203/801 ,  F23G2204/103 ,  F23G2900/54001 ,  F23J15/04

Abstract: A refuse incinerating oven includes a refuse loading car, and a furnace body with lower and upper combustion chambers. The car is conveyed through the furnace body such that refuse loaded on the car can be ignited in the lower combustion chamber. The combustion exhaust generated in the lower combustion chamber flows into and is heated in the upper combustion chamber. A spraying tank is communicated with the upper combustion chamber for receiving the combustion exhaust. Water mist is sprayed to the combustion exhaust in the spraying tank so as to generate aerated water. The aerated water and the combustion exhaust flowing from the spraying tank are cooled as they flow into a reservoir. The aerated water is pumped from the reservoir to an upper end of a waterfall tank so as to generate a downwardly cascading water stream inside the waterfall tank. An exhaust port unit is connected to the upper end of the waterfall tank for sucking and releasing the combustion exhaust.

Abstract translation: 垃圾焚烧炉包括垃圾装载车和具有下燃烧室和上燃烧室的炉体。 汽车被输送通过炉体，使得装载在汽车上的垃圾可以在下燃烧室中点燃。 在下燃烧室中产生的燃烧废气在上燃烧室中流入并被加热。 喷雾罐与上燃烧室连通以接收燃烧排气。 将水雾喷雾到喷雾槽中的燃烧排气中，以产生充气水。 充气水和从喷射槽流出的燃烧废气在流入储存器时被冷却。 充气的水从储存器被泵送到瀑布罐的上端，以便在瀑布箱内产生向下的级联的水流。 排气口单元连接到瀑布箱的上端，用于吸入和释放燃烧排气。

公开(公告)号：US6035387A

公开(公告)日：2000-03-07

申请号：US324236

申请日：1999-06-02

Applicant: Chia-Chang Hsu ,  Ruey-Liang Ma ,  Chien-kuo Tien ,  Kun-Cheng Wu

Inventor： Chia-Chang Hsu ,  Ruey-Liang Ma ,  Chien-kuo Tien ,  Kun-Cheng Wu

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3806 ,  G06F9/30149 ,  G06F9/3804 ,  G06F9/3816 ,  G06F9/3844

Abstract: A processor architecture is disclosed including a fetcher, packet unit and branch target buffer. The branch target buffer is provided with a tag RAM that is organized in a set associative fashion. In response to receiving a search address, multiple sets in the tag RAM are simultaneously searched for a branch instruction that is predicted to be taken. The packet unit has a queue into which fetched cache blocks are stored containing instructions. Sequentially fetched cache blocks are stored in adjacent locations of the queue. The queue entries also have indicators that indicate whether or not a starting or final data word of an instruction sequence is contained in the queue entry and if so, an offset indicating the particular starting or final data word. In response, the packet unit concatenates data words of an instruction sequence into contiguous blocks. The fetcher generates a fetch address for fetching a cache block from the instruction cache containing instructions to be executed. The fetcher also generates a search address for output to the branch target buffer. In response to the branch target buffer detecting a taken branch that crosses multiple cache blocks, the fetch address is increased so that it points to the next cache block to be fetched but the search address is maintained the same.

Abstract translation: 公开了一种处理器架构，包括一个提取器，分组单元和分支目标缓冲器。 分支目标缓冲器设置有以组合关联方式组织的标签RAM。 响应于接收到搜索地址，标签RAM中的多个集合被同时搜索预测要被采用的分支指令。 分组单元具有存储包含指令的获取的高速缓存块的队列。 顺序获取的高速缓存块存储在队列的相邻位置。 队列条目还具有指示指示序列的起始或最终数据字是否包含在队列条目中的指示符，如果是，则指示特定起始数据字或最终数据字的偏移量。 作为响应，分组单元将指令序列的数据字连接成连续的块。 提取器产生一个取出地址，用于从包含要执行的指令的指令高速缓存中提取缓存块。 读取器还生成用于输出到分支目标缓冲区的搜索地址。 响应于分支目标缓冲器检测跨越多个高速缓存块的被采取的分支，提取地址增加，使得它指向要获取的下一个高速缓存块，但是搜索地址保持相同。

公开(公告)号：US07131079B2

公开(公告)日：2006-10-31

申请号：US10839534

申请日：2004-05-04

Applicant: Kun-Cheng Wu ,  Chien-Ming Huang ,  Chang-Chung Wu

Inventor： Kun-Cheng Wu ,  Chien-Ming Huang ,  Chang-Chung Wu

IPC: G06F17/50

CPC classification number: G06F17/5022

Abstract: A method of generating a protected standard delay format (SDF) file is disclosed. The interconnect delay descriptions of a SDF file are backwardly or forwardly integrated into the related cell delay descriptions according to their interconnection type to generate the protected SDF file. The total delay value of each signal path is the same as original, so that the simulation result generated by a simulator is not affected.

Abstract translation: 公开了一种生成受保护的标准延迟格式（SDF）文件的方法。 SDF文件的互连延迟描述根据其互连类型向后或向前集成到相关的单元延迟描述中，以生成受保护的SDF文件。 每个信号路径的总延迟值与原始路径相同，因此模拟器产生的仿真结果不受影响。

公开(公告)号：US20050177806A1

公开(公告)日：2005-08-11

申请号：US10710420

申请日：2004-07-09

Applicant: Kun-Cheng Wu ,  Chien-Ming Huang

Inventor： Kun-Cheng Wu ,  Chien-Ming Huang

IPC: G06F17/50

CPC classification number: G06F17/5045

Abstract: A method for reducing standard delay format (SDF) file size is disclosed. The state-dependent descriptions in cell descriptions of the SDF file, which are impossible to be used, are removed by referring to a design description of an integrated circuit design. Therefore, the SDF file size is reduced and the simulation result generated by a simulator is not affected with the reduced SDF file.

Abstract translation: 公开了一种降低标准延迟格式（SDF）文件大小的方法。 通过参考集成电路设计的设计描述，可以去除不可能使用的SDF文件的单元描述中的状态相关描述。 因此，减少了SDF文件大小，并且模拟器生成的仿真结果不受缩小的SDF文件的影响。

公开(公告)号：US20050251764A1

公开(公告)日：2005-11-10

申请号：US10839534

申请日：2004-05-04

Applicant: Kun-Cheng Wu ,  Jimmy Huang ,  David Wu

Inventor： Kun-Cheng Wu ,  Jimmy Huang ,  David Wu

IPC: G06F17/50

CPC classification number: G06F17/5022

Abstract: A method of generating a protected standard delay format (SDF) file is disclosed. The interconnect delay descriptions of a SDF file are backwardly or forwardly integrated into the related cell delay descriptions according to their interconnection type to generate the protected SDF file. The total delay value of each signal path is the same as original, so that the simulation result generated by a simulator is not affected.

Abstract translation: 公开了一种生成受保护的标准延迟格式（SDF）文件的方法。 SDF文件的互连延迟描述根据其互连类型向后或向前集成到相关的单元延迟描述中，以生成受保护的SDF文件。 每个信号路径的总延迟值与原始路径相同，因此模拟器产生的仿真结果不受影响。