公开(公告)号：US07131079B2

公开(公告)日：2006-10-31

申请号：US10839534

申请日：2004-05-04

Applicant: Kun-Cheng Wu ,  Chien-Ming Huang ,  Chang-Chung Wu

Inventor： Kun-Cheng Wu ,  Chien-Ming Huang ,  Chang-Chung Wu

IPC: G06F17/50

CPC classification number: G06F17/5022

Abstract: A method of generating a protected standard delay format (SDF) file is disclosed. The interconnect delay descriptions of a SDF file are backwardly or forwardly integrated into the related cell delay descriptions according to their interconnection type to generate the protected SDF file. The total delay value of each signal path is the same as original, so that the simulation result generated by a simulator is not affected.

Abstract translation: 公开了一种生成受保护的标准延迟格式（SDF）文件的方法。 SDF文件的互连延迟描述根据其互连类型向后或向前集成到相关的单元延迟描述中，以生成受保护的SDF文件。 每个信号路径的总延迟值与原始路径相同，因此模拟器产生的仿真结果不受影响。

公开(公告)号：US20050177806A1

公开(公告)日：2005-08-11

申请号：US10710420

申请日：2004-07-09

Applicant: Kun-Cheng Wu ,  Chien-Ming Huang

Inventor： Kun-Cheng Wu ,  Chien-Ming Huang

IPC: G06F17/50

CPC classification number: G06F17/5045

Abstract: A method for reducing standard delay format (SDF) file size is disclosed. The state-dependent descriptions in cell descriptions of the SDF file, which are impossible to be used, are removed by referring to a design description of an integrated circuit design. Therefore, the SDF file size is reduced and the simulation result generated by a simulator is not affected with the reduced SDF file.

Abstract translation: 公开了一种降低标准延迟格式（SDF）文件大小的方法。 通过参考集成电路设计的设计描述，可以去除不可能使用的SDF文件的单元描述中的状态相关描述。 因此，减少了SDF文件大小，并且模拟器生成的仿真结果不受缩小的SDF文件的影响。

公开(公告)号：US07290231B2

公开(公告)日：2007-10-30

申请号：US10710420

申请日：2004-07-09

Applicant: Kun-Cheng Wu ,  Chien-Ming Huang

Inventor： Kun-Cheng Wu ,  Chien-Ming Huang

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F17/5045

Abstract: A method for reducing standard delay format (SDF) file size is disclosed. The state-dependent descriptions in cell descriptions of the SDF file, which are not intended to be used, are removed by referring to a design description of an integrated circuit design. Therefore, the SDF file size is reduced and the simulation result generated by a simulator is not affected with the reduced SDF file.

Abstract translation: 公开了一种降低标准延迟格式（SDF）文件大小的方法。 通过参考集成电路设计的设计描述来去除不想使用的SDF文件的单元描述中的状态相关描述。 因此，减少了SDF文件大小，并且模拟器生成的仿真结果不受缩小的SDF文件的影响。

公开(公告)号：US20080141198A1

公开(公告)日：2008-06-12

申请号：US11608248

申请日：2006-12-08

Applicant: Hanping Chen ,  Chih-Yang Peng ,  Alvin Hsin-Hung Chen ,  Jia-Jio Huang ,  Jim Jyh-Herng Wang ,  Kun-Cheng Wu

Inventor： Hanping Chen ,  Chih-Yang Peng ,  Alvin Hsin-Hung Chen ,  Jia-Jio Huang ,  Jim Jyh-Herng Wang ,  Kun-Cheng Wu

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: A fast methodology and system to characterize setup/hold time for analog IPs are provided. Partial circuits of clock and data paths are simulated instead of the simulation of entire IPs. The partial circuits include all those paths of clock pin and data input pins before reaching first level DFF. This methodology includes multi-path searching of hierarchical SPICE netlist for the path of clock pin and data pins, so as to reduce the circuit subset, merge the paths of clock pin and the data pins, and characterize the setup/hold time for the analog IP. The paths of data pins and clock pin before DFF are used for setup/hold time characterization.

Abstract translation: 提供了一种用于表征模拟IP的设置/保持时间的快速方法和系统。 模拟时钟和数据路径的部分电路，而不是整个IP的仿真。 部分电路包括达到第一级DFF之前的时钟引脚和数据输入引脚的所有路径。 该方法包括多路径搜索时钟引脚和数据引脚路径的分层SPICE网表，以减少电路子集，合并时钟引脚和数据引脚的路径，并表征模拟的建立/保持时间 IP。 DFF之前的数据引脚和时钟引脚的路径用于建立/保持时间表征。

公开(公告)号：US5948100A

公开(公告)日：1999-09-07

申请号：US972226

申请日：1997-11-17

Applicant: Chia-Chang Hsu ,  Ruey-Liang Ma ,  Chien-Kuo Tien ,  Kun-Cheng Wu

Inventor： Chia-Chang Hsu ,  Ruey-Liang Ma ,  Chien-Kuo Tien ,  Kun-Cheng Wu

IPC: G06F9/30 ,  G06F9/38 ,  G06F13/00

CPC classification number: G06F9/3806 ,  G06F9/30149 ,  G06F9/3804 ,  G06F9/3816 ,  G06F9/3844

Abstract: A processor architecture is disclosed including a fetcher, packet unit and branch target buffer. The branch target buffer is provided with a tag RAM that is organized in a set associative fashion. In response to receiving a search address, multiple sets in the tag RAM are simultaneously searched for a branch instruction that is predicted to be taken. The packet unit has a queue into which fetched cache blocks are stored containing instructions. Sequentially fetched cache blocks are stored in adjacent locations of the queue. The queue entries also have indicators that indicate whether or not a starting or final data word of an instruction sequence is contained in the queue entry and if so, an offset indicating the particular starting or final data word. In response, the packet unit concatenates data words of an instruction sequence into contiguous blocks. The fetcher generates a fetch address for fetching a cache block from the instruction cache containing instructions to be executed. The fetcher also generates a search address for output to the branch target buffer. In response to the branch target buffer detecting a taken branch that crosses multiple cache blocks, the fetch address is increased so that it points to the next cache block to be fetched but the search address is maintained the same.

Abstract translation: 公开了一种处理器架构，包括一个提取器，分组单元和分支目标缓冲器。 分支目标缓冲器设置有以组合关联方式组织的标签RAM。 响应于接收到搜索地址，标签RAM中的多个集合被同时搜索预测要被采用的分支指令。 分组单元具有包含指令的被存储的高速缓存块所存储的队列。 顺序获取的高速缓存块存储在队列的相邻位置。 队列条目还具有指示指示序列的起始或最终数据字是否包含在队列条目中的指示符，如果是，则指示特定起始数据字或最终数据字的偏移量。 作为响应，分组单元将指令序列的数据字连接成连续的块。 提取器产生一个取出地址，用于从包含要执行的指令的指令高速缓存中提取缓存块。 读取器还生成用于输出到分支目标缓冲区的搜索地址。 响应于分支目标缓冲器检测跨越多个高速缓存块的取得的分支，提取地址增加，使得它指向要获取的下一个高速缓存块，但是搜索地址保持相同。

公开(公告)号：US20050251764A1

公开(公告)日：2005-11-10

申请号：US10839534

申请日：2004-05-04

Applicant: Kun-Cheng Wu ,  Jimmy Huang ,  David Wu

Inventor： Kun-Cheng Wu ,  Jimmy Huang ,  David Wu

IPC: G06F17/50

CPC classification number: G06F17/5022

Abstract: A method of generating a protected standard delay format (SDF) file is disclosed. The interconnect delay descriptions of a SDF file are backwardly or forwardly integrated into the related cell delay descriptions according to their interconnection type to generate the protected SDF file. The total delay value of each signal path is the same as original, so that the simulation result generated by a simulator is not affected.

Abstract translation: 公开了一种生成受保护的标准延迟格式（SDF）文件的方法。 SDF文件的互连延迟描述根据其互连类型向后或向前集成到相关的单元延迟描述中，以生成受保护的SDF文件。 每个信号路径的总延迟值与原始路径相同，因此模拟器产生的仿真结果不受影响。

公开(公告)号：US06258274B1

公开(公告)日：2001-07-10

申请号：US09610180

申请日：2000-07-05

Applicant: Kun-Cheng Wu

Inventor： Kun-Cheng Wu

IPC: C02F900

CPC classification number: C02F9/00 ,  B01D29/23 ,  C02F1/001 ,  C02F1/74 ,  C02F11/06 ,  C02F11/12 ,  C02F2301/043 ,  E02B3/023 ,  Y02A10/28 ,  Y02W10/40 ,  Y10S210/903

Abstract: A river is divided into a plurality of river sections via a plurality of partitions which are spaced apart along the direction of the flow of the river. Polluted water at or near the surface of the river from the river sections is pumped to water treating apparatuses without drawing the polluted water near the floor of the river. Suspension pollutants, including nitrogenous nutrients, are removed from the polluted water via filtration in the water treating apparatuses. After treatment, the treated water is sent to the river in such a manner that the water drawn from each river section is sent to another one of the river sections, that is located immediately downstream, at the same rate as the river flow and that the remaining portion of the treated water is sent back to the upstream river section from where the water comes. Successive removal of the suspension pollutants from the river sections results in releasing of nitrogenous nutrients from sludge on the floor of the river to upper parts of the river sections, thereby reducing the thickness of the sludge.

Abstract translation: 河流经由沿河流方向间隔开的多个隔板分成多个河段。 在河段或河流附近的河流表面的污染水被泵送到水处理设备，而不会在河流附近被污染的水。 在水处理装置中通过过滤从污染水中除去悬浮污染物，包括含氮营养物质。 处理后，处理后的水以每个河段抽水的方式送往河流，直接位于下游的另一条河段，河流流速相同， 被处理水的剩余部分被送回上游河段。 从河段连续清除悬浮污染物，导致河流地板上的污泥向河段上游释放含氮营养物质，从而减少污泥的厚度。

公开(公告)号：US5819308A

公开(公告)日：1998-10-06

申请号：US807297

申请日：1997-02-27

Applicant: Chien-Kuo Tien ,  Kun-Cheng Wu ,  Dze-Chaung Wang ,  Ching-Tang Chang

Inventor： Chien-Kuo Tien ,  Kun-Cheng Wu ,  Dze-Chaung Wang ,  Ching-Tang Chang

IPC: G06F9/38 ,  G06F12/00

CPC classification number: G06F9/3885 ,  G06F9/3836 ,  G06F9/3857

Abstract: An improved method and apparatus for buffering and issuing instructions for use with superscalar microprocessors are disclosed. The method comprises the steps of: (a) obtaining an instruction buffer comprising a plurality of entries, each entry comprising a random access memory (RAM) portion and a content addressable memory (CAM) portion for storing result data and source operand tag, respectively, wherein the CAM portion also contains means for linking with an associated RAM portion and the result data contains an instruction; (b) providing a result bus capable of transmitting the result data and a result tag; (c) matching the result tag in the result bus with the source operand tag in the CAM, and writing the result data into the RAM portion of an entry if the result tag in the result bus matches the source operand tag of an associated CAM portion; and (d) issuing ready instructions and changing the source operand tag in a corresponding CAM in such a manner that the entry containing the CAM will be identified as an empty entry so as to all new instruction to be written thereto. Because instructions are stored in the RAM in an out-of-order, a linear systolic array is provided so as to keep the sequence of instructions in order. The linear systolic array, which can be easily compressed, allows the prioritization of instructions for issue among ready instructions, and the handling branch mis-prediction and faults to be implemented.

Abstract translation: 公开了一种改进的用于缓冲和发出与超标量微处理器一起使用的指令的方法和装置。 该方法包括以下步骤：（a）获得包括多个条目的指令缓冲器，每个条目分别包括用于存储结果数据和源操作数标签的随机存取存储器（RAM）部分和内容寻址存储器（CAM）部分 ，其中所述CAM部分还包含用于与相关联的RAM部分链接的装置，并且所述结果数据包含指令; （b）提供能够发送结果数据和结果标签的结果总线; （c）将结果总线中的结果标签与CAM中的源操作数标签进行匹配，如果结果总线中的结果标签与相关联的CAM部分的源操作数标签匹配，则将结果数据写入条目的RAM部分 ; 以及（d）以相应CAM的方式发出就绪指令并更改源操作数标签，使得包含CAM的条目将被识别为空条目，以便将所有新的指令写入。 由于指令以无序的方式存储在RAM中，因此提供了线性收缩阵列，以便按顺序保持指令序列。 可以容易地压缩的线性收缩阵列允许在准备指令之间发出指令的优先次序，以及要实现的处理分支误预测和故障。

公开(公告)号：US10814199B1

公开(公告)日：2020-10-27

申请号：US16546443

申请日：2019-08-21

Applicant: Kun-Cheng Wu ,  Fan Chia

Inventor： Kun-Cheng Wu ,  Fan Chia

IPC: A63B69/00 ,  A63B63/08 ,  A63B71/06 ,  A63B63/00

Abstract: A basketball shooting training includes a stand, a rotatable hoop module, a blocking module, and a guide module. The stand includes a horizontal segment and a vertical segment. The rotatable hoop module includes a frame and a backboard. The blocking module includes two columns, a collection member, an obstruction unit, and two fixed pulley sets. The guide module includes a conducting device mounted on the horizontal segment of the stand, and the supply portion extends outward from the stand. The mounting of the stand is fixed on a bottom of the conducting device, and the rotatable hoop module further includes a support post on which the backboard is disposed. A movable seat is connected on a bottom of the support post, the movable seat is disposed on and rotates along the mounting, and the conducting device has an arcuate track on which the support post slides.

公开(公告)号：US07596772B2

公开(公告)日：2009-09-29

申请号：US11608248

申请日：2006-12-08

Applicant: Hanping Chen ,  Chih-Yang Peng ,  Alvin Hsin-Hung Chen ,  Jia-Jio Huang ,  Jim Jyh-Herng Wang ,  Kun-Cheng Wu

Inventor： Hanping Chen ,  Chih-Yang Peng ,  Alvin Hsin-Hung Chen ,  Jia-Jio Huang ,  Jim Jyh-Herng Wang ,  Kun-Cheng Wu

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F17/5036

Abstract: A fast methodology and system to characterize setup/hold time for analog IPs are provided. Partial circuits of clock and data paths are simulated instead of the simulation of entire IPs. The partial circuits include all those paths of clock pin and data input pins before reaching first level DFF. This methodology includes multi-path searching of hierarchical SPICE netlist for the path of clock pin and data pins, so as to reduce the circuit subset, merge the paths of clock pin and the data pins, and characterize the setup/hold time for the analog IP. The paths of data pins and clock pin before DFF are used for setup/hold time characterization.

Abstract translation: 提供了一种用于表征模拟IP的设置/保持时间的快速方法和系统。 模拟时钟和数据路径的部分电路，而不是整个IP的仿真。 部分电路包括达到第一级DFF之前的时钟引脚和数据输入引脚的所有路径。 该方法包括多路径搜索时钟引脚和数据引脚路径的分层SPICE网表，以减少电路子集，合并时钟引脚和数据引脚的路径，并表征模拟的建立/保持时间 IP。 DFF之前的数据引脚和时钟引脚的路径用于建立/保持时间表征。