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1.
公开(公告)号:US08530326B2
公开(公告)日:2013-09-10
申请号:US13538220
申请日:2012-06-29
申请人: Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng-Cheng , Chien-Hung Wu , Tzung-Chi Lee
发明人: Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng-Cheng , Chien-Hung Wu , Tzung-Chi Lee
IPC分类号: H01L21/76
CPC分类号: H01L21/823437 , H01L21/31053 , H01L21/3212 , H01L21/823828 , H01L27/08
摘要: A method of semiconductor device fabrication including forming a plurality of gate structures in a first portion of a substrate, wherein the plurality of gate structures have a first height. A first metal gate structure is formed in a second portion of the substrate, the first metal gate structure being surrounded by an isolation region. A plurality of dummy gate structures is formed in the second portion of the substrate. The plurality of dummy gate structures are configured in a ring formation encircling the metal gate structure and the isolation region. The plurality of dummy structures have a top surface that is substantially planar with the plurality of gate structures and covers at least 5% of a pattern density of the second portion of the substrate.
摘要翻译: 一种半导体器件制造方法,包括在衬底的第一部分中形成多个栅极结构,其中所述多个栅极结构具有第一高度。 第一金属栅极结构形成在衬底的第二部分中,第一金属栅极结构被隔离区包围。 在基板的第二部分中形成多个虚拟栅极结构。 多个虚拟栅极结构被构造成围绕金属栅极结构和隔离区域的环形结构。 多个虚拟结构具有与多个栅极结构基本平面的顶表面,并且覆盖基板的第二部分的图案密度的至少5%。
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公开(公告)号:US08237227B2
公开(公告)日:2012-08-07
申请号:US12455509
申请日:2009-06-03
申请人: Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
发明人: Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
IPC分类号: H01L21/70
CPC分类号: H01L21/823437 , H01L21/31053 , H01L21/3212 , H01L21/823828 , H01L27/08
摘要: A semiconductor device is provided which includes a semiconductor substrate having a first portion and a second portion, transistors formed in the first portion of the substrate, each transistor having a gate structure with a high-k dielectric and a metal gate, a device element formed in the second portion of the substrate, the device element being isolated by an isolation region, and a polishing stopper formed adjacent the isolation region and having a surface that is substantially planar with a surface of the gate structures of the transistors in the first region.
摘要翻译: 提供一种半导体器件,其包括具有第一部分和第二部分的半导体衬底,形成在衬底的第一部分中的晶体管,每个晶体管具有具有高k电介质和金属栅极的栅极结构,形成器件元件 在衬底的第二部分中,器件元件被隔离区域隔离,抛光停止件形成在隔离区域附近,并且具有与第一区域中的晶体管的栅极结构的表面基本平面的表面。
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公开(公告)号:US20100052060A1
公开(公告)日:2010-03-04
申请号:US12455509
申请日:2009-06-03
申请人: Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
发明人: Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
CPC分类号: H01L21/823437 , H01L21/31053 , H01L21/3212 , H01L21/823828 , H01L27/08
摘要: A semiconductor device is provided which includes a semiconductor substrate having a first portion and a second portion, transistors formed in the first portion of the substrate, each transistor having a gate structure with a high-k dielectric and a metal gate, a device element formed in the second portion of the substrate, the device element being isolated by an isolation region, and a polishing stopper formed adjacent the isolation region and having a surface that is substantially planar with a surface of the gate structures of the transistors in the first region.
摘要翻译: 提供一种半导体器件,其包括具有第一部分和第二部分的半导体衬底,形成在衬底的第一部分中的晶体管,每个晶体管具有具有高k电介质和金属栅极的栅极结构,形成器件元件 在衬底的第二部分中,器件元件被隔离区域隔离,抛光停止件形成在隔离区域附近,并且具有与第一区域中的晶体管的栅极结构的表面基本平面的表面。
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4.
公开(公告)号:US20120270379A1
公开(公告)日:2012-10-25
申请号:US13538220
申请日:2012-06-29
申请人: Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
发明人: Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
IPC分类号: H01L21/76
CPC分类号: H01L21/823437 , H01L21/31053 , H01L21/3212 , H01L21/823828 , H01L27/08
摘要: A method of semiconductor device fabrication including forming a plurality of gate structures in a first portion of a substrate, wherein the plurality of gate structures have a first height. A first metal gate structure is formed in a second portion of the substrate, the first metal gate structure being surrounded by an isolation region. A plurality of dummy gate structures is formed in the second portion of the substrate. The plurality of dummy gate structures are configured in a ring formation encircling the metal gate structure and the isolation region. The plurality of dummy structures have a top surface that is substantially planar with the plurality of gate structures and covers at least 5% of a pattern density of the second portion of the substrate.
摘要翻译: 一种半导体器件制造方法,包括在衬底的第一部分中形成多个栅极结构,其中所述多个栅极结构具有第一高度。 第一金属栅极结构形成在衬底的第二部分中,第一金属栅极结构被隔离区包围。 在基板的第二部分中形成多个虚拟栅极结构。 多个虚拟栅极结构被构造成围绕金属栅极结构和隔离区域的环形结构。 多个虚拟结构具有与多个栅极结构基本平面的顶表面,并且覆盖基板的第二部分的图案密度的至少5%。
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