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46 条记录 (耗时 0.042 秒)

    Integrating a first contact structure in a gate last process
    7.
    发明授权
    Integrating a first contact structure in a gate last process 有权
    在最后一个进程中集成第一个接触结构

    公开(公告)号：US08035165B2

    公开(公告)日：2011-10-11

    申请号：US12341891

    申请日：2008-12-22

    申请人： Chiung-Han Yeh ,  Ming-Yuan Wu ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

    发明人： Chiung-Han Yeh ,  Ming-Yuan Wu ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/66606 ,  H01L21/823814 ,  H01L21/823871

    摘要： A semiconductor device is provided which includes a semiconductor substrate, a transistor formed on the substrate, the transistor having a gate stack including a metal gate and high-k gate dielectric and a dual first contact formed on the substrate. The dual first contact includes a first contact feature, a second contact feature overlying the first contact feature, and a metal barrier formed on sidewalls and bottom of the second contact feature, the metal barrier layer coupling the first contact feature to the second contact feature.

    摘要翻译： 提供一种半导体器件，其包括半导体衬底，形成在衬底上的晶体管，晶体管具有包括金属栅极和高k栅极电介质的栅极堆叠以及形成在衬底上的双重第一接触。 所述双重第一接触包括第一接触特征，覆盖所述第一接触特征的第二接触特征以及形成在所述第二接触特征的侧壁和底部上的金属屏障，所述金属阻挡层将所述第一接触特征耦合到所述第二接触特征。

    Photo alignment mark for a gate last process
    8.
    发明授权
    Photo alignment mark for a gate last process 有权
    最后一个进程的照片对齐标记

    公开(公告)号：US08598630B2

    公开(公告)日：2013-12-03

    申请号：US12470333

    申请日：2009-05-21

    申请人： Gary Shen ,  Ming-Yuan Wu ,  Chiung-Han Yeh ,  Kong-Beng Thei ,  Harry Chuang

    发明人： Gary Shen ,  Ming-Yuan Wu ,  Chiung-Han Yeh ,  Kong-Beng Thei ,  Harry Chuang

    IPC分类号： H01L23/52

    CPC分类号： H01L23/544 ,  H01L21/31051 ,  H01L21/823828 ,  H01L23/585 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device is provided which includes a semiconductor substrate having a first region and a second region, the first and second regions being isolated from each other, a plurality of transistors formed in the first region, an alignment mark formed in the second region, the alignment mark having a plurality of active regions in a first direction, and a dummy gate structure formed over the alignment mark, the dummy gate structure having a plurality of lines in a second direction different from the first direction.

    摘要翻译： 提供一种半导体器件，其包括具有第一区域和第二区域的半导体衬底，第一和第二区域彼此隔离，形成在第一区域中的多个晶体管，形成在第二区域中的对准标记， 对准标记具有在第一方向上的多个有效区域，以及形成在所述对准标记上的伪栅极结构，所述伪栅极结构在与所述第一方向不同的第二方向上具有多条线。

    Dishing-free gap-filling with multiple CMPs
    9.
    发明授权
    Dishing-free gap-filling with multiple CMPs 有权

    公开(公告)号：US08552522B2

    公开(公告)日：2013-10-08

    申请号：US13151666

    申请日：2011-06-02

    申请人： Ming-Yuan Wu ,  Kong-Beng Thei ,  Chiung-Han Yeh ,  Harry Chuang ,  Mong-Song Liang

    发明人： Ming-Yuan Wu ,  Kong-Beng Thei ,  Chiung-Han Yeh ,  Harry Chuang ,  Mong-Song Liang

    IPC分类号： H01L21/70

    CPC分类号： H01L21/76883 ,  H01L21/76229

    摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.