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1.
公开(公告)号:US20120270379A1
公开(公告)日:2012-10-25
申请号:US13538220
申请日:2012-06-29
申请人: Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
发明人: Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
IPC分类号: H01L21/76
CPC分类号: H01L21/823437 , H01L21/31053 , H01L21/3212 , H01L21/823828 , H01L27/08
摘要: A method of semiconductor device fabrication including forming a plurality of gate structures in a first portion of a substrate, wherein the plurality of gate structures have a first height. A first metal gate structure is formed in a second portion of the substrate, the first metal gate structure being surrounded by an isolation region. A plurality of dummy gate structures is formed in the second portion of the substrate. The plurality of dummy gate structures are configured in a ring formation encircling the metal gate structure and the isolation region. The plurality of dummy structures have a top surface that is substantially planar with the plurality of gate structures and covers at least 5% of a pattern density of the second portion of the substrate.
摘要翻译: 一种半导体器件制造方法,包括在衬底的第一部分中形成多个栅极结构,其中所述多个栅极结构具有第一高度。 第一金属栅极结构形成在衬底的第二部分中,第一金属栅极结构被隔离区包围。 在基板的第二部分中形成多个虚拟栅极结构。 多个虚拟栅极结构被构造成围绕金属栅极结构和隔离区域的环形结构。 多个虚拟结构具有与多个栅极结构基本平面的顶表面,并且覆盖基板的第二部分的图案密度的至少5%。
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公开(公告)号:US08237227B2
公开(公告)日:2012-08-07
申请号:US12455509
申请日:2009-06-03
申请人: Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
发明人: Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
IPC分类号: H01L21/70
CPC分类号: H01L21/823437 , H01L21/31053 , H01L21/3212 , H01L21/823828 , H01L27/08
摘要: A semiconductor device is provided which includes a semiconductor substrate having a first portion and a second portion, transistors formed in the first portion of the substrate, each transistor having a gate structure with a high-k dielectric and a metal gate, a device element formed in the second portion of the substrate, the device element being isolated by an isolation region, and a polishing stopper formed adjacent the isolation region and having a surface that is substantially planar with a surface of the gate structures of the transistors in the first region.
摘要翻译: 提供一种半导体器件,其包括具有第一部分和第二部分的半导体衬底,形成在衬底的第一部分中的晶体管,每个晶体管具有具有高k电介质和金属栅极的栅极结构,形成器件元件 在衬底的第二部分中,器件元件被隔离区域隔离,抛光停止件形成在隔离区域附近,并且具有与第一区域中的晶体管的栅极结构的表面基本平面的表面。
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公开(公告)号:US20100052060A1
公开(公告)日:2010-03-04
申请号:US12455509
申请日:2009-06-03
申请人: Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
发明人: Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
CPC分类号: H01L21/823437 , H01L21/31053 , H01L21/3212 , H01L21/823828 , H01L27/08
摘要: A semiconductor device is provided which includes a semiconductor substrate having a first portion and a second portion, transistors formed in the first portion of the substrate, each transistor having a gate structure with a high-k dielectric and a metal gate, a device element formed in the second portion of the substrate, the device element being isolated by an isolation region, and a polishing stopper formed adjacent the isolation region and having a surface that is substantially planar with a surface of the gate structures of the transistors in the first region.
摘要翻译: 提供一种半导体器件,其包括具有第一部分和第二部分的半导体衬底,形成在衬底的第一部分中的晶体管,每个晶体管具有具有高k电介质和金属栅极的栅极结构,形成器件元件 在衬底的第二部分中,器件元件被隔离区域隔离,抛光停止件形成在隔离区域附近,并且具有与第一区域中的晶体管的栅极结构的表面基本平面的表面。
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4.
公开(公告)号:US08530326B2
公开(公告)日:2013-09-10
申请号:US13538220
申请日:2012-06-29
申请人: Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng-Cheng , Chien-Hung Wu , Tzung-Chi Lee
发明人: Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng-Cheng , Chien-Hung Wu , Tzung-Chi Lee
IPC分类号: H01L21/76
CPC分类号: H01L21/823437 , H01L21/31053 , H01L21/3212 , H01L21/823828 , H01L27/08
摘要: A method of semiconductor device fabrication including forming a plurality of gate structures in a first portion of a substrate, wherein the plurality of gate structures have a first height. A first metal gate structure is formed in a second portion of the substrate, the first metal gate structure being surrounded by an isolation region. A plurality of dummy gate structures is formed in the second portion of the substrate. The plurality of dummy gate structures are configured in a ring formation encircling the metal gate structure and the isolation region. The plurality of dummy structures have a top surface that is substantially planar with the plurality of gate structures and covers at least 5% of a pattern density of the second portion of the substrate.
摘要翻译: 一种半导体器件制造方法,包括在衬底的第一部分中形成多个栅极结构,其中所述多个栅极结构具有第一高度。 第一金属栅极结构形成在衬底的第二部分中,第一金属栅极结构被隔离区包围。 在基板的第二部分中形成多个虚拟栅极结构。 多个虚拟栅极结构被构造成围绕金属栅极结构和隔离区域的环形结构。 多个虚拟结构具有与多个栅极结构基本平面的顶表面,并且覆盖基板的第二部分的图案密度的至少5%。
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5.
公开(公告)号:US20160095231A1
公开(公告)日:2016-03-31
申请号:US14603363
申请日:2015-01-23
申请人: Chien-Hung Wu
发明人: Chien-Hung Wu
IPC分类号: H05K3/46
CPC分类号: H05K3/4697 , H05K3/4614 , H05K3/462 , H05K3/4644 , H05K3/465 , H05K2203/061 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913
摘要: A manufacturing method of a multi-layer circuit board having a cavity is provided, including the following steps: a core board is provided, and a through hole is formed penetrating the core board; two build-up structures are bonded to two opposite sides of the core board to foam the multi-layer circuit board, and the two build-up structures cover the through hole; and a portion of one of the two build-up structures corresponding to the through hole is removed to make the through hole communicate with the outside and form the cavity. A multi-layer circuit board having a cavity, manufactured by the aforementioned method, is also provided.
摘要翻译: 提供一种具有空腔的多层电路板的制造方法,包括以下步骤:设置芯板,并且形成穿透芯板的通孔; 两个堆积结构被结合到芯板的两个相对侧以使多层电路板发泡,并且两个堆积结构覆盖通孔; 并且去除与通孔相对应的两个堆积结构中的一个的一部分,以使通孔与外部连通并形成空腔。 还提供了通过上述方法制造的具有空腔的多层电路板。
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公开(公告)号:USD716248S1
公开(公告)日:2014-10-28
申请号:US29432674
申请日:2012-09-19
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7.
公开(公告)号:US07904636B2
公开(公告)日:2011-03-08
申请号:US11358673
申请日:2006-02-21
申请人: Chien-Hung Wu
发明人: Chien-Hung Wu
IPC分类号: G06F12/10
CPC分类号: G06F3/0616 , G06F3/064 , G06F3/0679 , G06F12/0246
摘要: A memory and storage device includes a data management system for transferring data units referenced by logical addresses. The data management system maps the logical addresses to sequential virtual addresses according to the order the data units are received. The data management system also maps the sequential virtual addresses to sequential physical addresses in a memory block of a memory device. Additionally, the data management system can modify a data unit in the memory block by copying any other valid data units in the memory block to another memory block and writing the modified data unit into this other memory block. The data management system writes the valid data units and the modified data unit into sequential physical addresses of this other memory block.
摘要翻译: 存储器和存储设备包括用于传送由逻辑地址引用的数据单元的数据管理系统。 数据管理系统根据接收数据单元的顺序将逻辑地址映射到顺序虚拟地址。 数据管理系统还将顺序虚拟地址映射到存储器件的存储器块中的顺序物理地址。 此外,数据管理系统可以通过将存储器块中的任何其他有效数据单元复制到另一个存储块并将修改的数据单元写入该另一个存储器块来修改存储器块中的数据单元。 数据管理系统将有效的数据单元和修改的数据单元写入该另一个存储块的顺序物理地址。
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公开(公告)号:USD595289S1
公开(公告)日:2009-06-30
申请号:US29321870
申请日:2008-07-24
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公开(公告)号:US20070246786A1
公开(公告)日:2007-10-25
申请号:US11407853
申请日:2006-04-19
申请人: Jeffrey Melzak , Chien-Hung Wu
发明人: Jeffrey Melzak , Chien-Hung Wu
CPC分类号: B81C1/00666 , H01L21/3148 , H01L29/1608 , H01L29/84 , Y10S438/931
摘要: Doped silicon carbide structures, as well as methods associated with the same, are provided. The structures, for example, are components (e.g., layer, patterned structure) in MEMS structures. The doped silicon carbide structures may be highly conductive, thus, providing low resistance to electrical current. An in-situ doping process may be used to form the structures. The process parameters can be selected so that the structures have a low residual stress and/or low strain gradient. Thus, the structures may be formed having desired dimensions with little (or no) distortion arising from residual stress and/or strain gradient. The high conductivity and mechanical integrity of the structures are significant advantages in MEMS devices such as sensors and actuators.
摘要翻译: 提供了掺杂的碳化硅结构,以及与其相关的方法。 该结构例如是MEMS结构中的部件(例如,层,图案化结构)。 掺杂的碳化硅结构可以是高导电性的,因此提供低电阻的电流。 可以使用原位掺杂工艺来形成结构。 可以选择工艺参数,使得结构具有低残余应力和/或低应变梯度。 因此,可以形成具有由残余应力和/或应变梯度引起的很少(或不)变形的期望尺寸的结构。 结构的高导电性和机械完整性在诸如传感器和致动器的MEMS装置中是显着的优点。
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公开(公告)号:US07194596B2
公开(公告)日:2007-03-20
申请号:US10863210
申请日:2004-06-09
申请人: Chien-Hung Wu , Jen-Chieh Lou , Chien-Hua Chu , Jui-Chien Chen
发明人: Chien-Hung Wu , Jen-Chieh Lou , Chien-Hua Chu , Jui-Chien Chen
IPC分类号: G06F12/00
CPC分类号: G06F12/0246 , G06F2212/7203
摘要: A data management for a flash memory device is disclosed. The device includes a screen virtual sector table and a virtual unit versus physical unit table (V2P table) for each block. With the auxiliary of the screen virtual sector table and v2p table, the data programming into the target block of the flash memory is in accordance with the data receiving order, which is from lower page number to higher page number in case the target block is free. The data can be written into the target block contains data already through one or two temporal block(s). The conventional LBA data transfer protocol can still be applied to the flash memory device of this invention.
摘要翻译: 公开了一种用于闪速存储器件的数据管理。 该装置包括用于每个块的屏幕虚拟扇区表和虚拟单元对物理单元表(V2P表)。 通过屏幕虚拟扇区表和v2p表的辅助,闪存中目标块的数据编程符合数据接收顺序,即从目标块空闲的页数到较高页数 。 可以将数据写入包含已经通过一个或两个时间块的数据的目标块。 传统的LBA数据传输协议仍然可以应用于本发明的闪存设备。
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