公开(公告)号：US08659121B2

公开(公告)日：2014-02-25

申请号：US13188343

申请日：2011-07-21

申请人： Kuo-Chi Tu ,  Kuo-Chyuan Tzeng ,  Wen-Chuan Chiang ,  Chen-Jong Wang

发明人： Kuo-Chi Tu ,  Kuo-Chyuan Tzeng ,  Wen-Chuan Chiang ,  Chen-Jong Wang

IPC分类号： H01L23/62

CPC分类号： H01L27/0207 ,  H01L28/40

摘要： Semiconductor devices with orientation-free decoupling capacitors and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes at least one integrated circuit and at least one decoupling capacitor. The at least one decoupling capacitor is oriented in a different direction than the at least one integrated circuit is oriented.

摘要翻译： 公开了具有无取向去耦电容器的半导体器件及其制造方法。 在一个实施例中，半导体器件包括至少一个集成电路和至少一个去耦电容器。 至少一个去耦电容器被定向在与至少一个集成电路取向的方向不同的方向上。

公开(公告)号：US08604531B2

公开(公告)日：2013-12-10

申请号：US12905523

申请日：2010-10-15

申请人： Kuo-Chi Tu

发明人： Kuo-Chi Tu

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L23/5223 ,  H01L27/10811 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate, an isolation structure disposed in the semiconductor substrate, a conductive layer disposed over the isolation structure, a capacitor disposed over the isolation structure, the capacitor including a top electrode, a bottom electrode, and a dielectric disposed between the top electrode and the bottom electrode, and a first contact electrically coupling the conductive layer and the bottom electrode, the bottom electrode substantially engaging the first contact on at least two faces.

摘要翻译： 半导体器件包括半导体衬底，设置在半导体衬底中的隔离结构，设置在隔离结构上的导电层，设置在隔离结构上的电容器，电容器包括顶电极，底电极和介于 所述顶部电极和所述底部电极以及将所述导电层和所述底部电极电耦合的第一接触件，所述底部电极在至少两个面上基本接合所述第一接触。

公开(公告)号：US08436408B2

公开(公告)日：2013-05-07

申请号：US12212096

申请日：2008-09-17

申请人： Kuo-Chi Tu ,  Huey-Chi Chu ,  Kuo-Cheng Ching

发明人： Kuo-Chi Tu ,  Huey-Chi Chu ,  Kuo-Cheng Ching

IPC分类号： H01L27/108

CPC分类号： H01L23/5223 ,  H01L27/0629 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes a circuit module having a plurality of active components coupled between a pair of supply nodes, and a capacitive decoupling module coupled to the circuit module. The capacitive decoupling module includes a plurality of metal-insulator-metal (MiM) capacitors coupled in series between the pair of supply nodes, wherein a voltage between the supply nodes is divided across the plurality of MiM capacitors, thereby reducing voltage stress on the capacitors.

摘要翻译： 集成电路包括具有耦合在一对电源节点之间的多个有源元件的电路模块和耦合到电路模块的电容去耦模块。 电容去耦模块包括串联耦合在一对电源节点之间的多个金属 - 绝缘体 - 金属（MiM）电容器，其中供电节点之间的电压在多个MiM电容器之间分开，从而减小电容器上的电压应力 。

公开(公告)号：US08232587B2

公开(公告)日：2012-07-31

申请号：US12683224

申请日：2010-01-06

申请人： Kuo-Chi Tu

发明人： Kuo-Chi Tu

IPC分类号： H01L29/94

CPC分类号： H01L28/86 ,  H01L27/10817 ,  H01L27/10852

摘要： A method of forming a metal-insulator-metal capacitor has the following steps. A stack dielectric structure is formed by alternately depositing a plurality of second dielectric layers and a plurality of third dielectric layers. A wet etch selectivity of the second dielectric layer relative to said third dielectric layer is of at least 5:1. An opening is formed in the stack dielectric structure, and then a wet etch process is employed to remove relatively-large portions of the second dielectric layers and relatively-small portions of the third dielectric layers to form a plurality of lateral recesses in the second dielectric layers along sidewalls of the opening. A bottom electrode layer is formed to extend along the serrate sidewalls, a capacitor dielectric layer is formed on the bottom electrode layer, and a top electrode layer is formed on the capacitor dielectric layer.

摘要翻译： 金属 - 绝缘体 - 金属电容器的形成方法如下。 通过交替地沉积多个第二电介质层和多个第三电介质层来形成堆叠电介质结构。 第二电介质层相对于所述第三电介质层的湿蚀刻选择性为至少5:1。 在堆叠电介质结构中形成开口，然后采用湿式蚀刻工艺来除去第二电介质层的相对大的部分和第三电介质层的相对较小的部分，以在第二电介质中形成多个横向凹槽 沿着开口的侧壁的层。 形成底电极层沿着锯齿状侧壁延伸，在底电极层上形成电容电介质层，在电容介电层上形成顶电极层。

公开(公告)号：US20100224925A1

公开(公告)日：2010-09-09

申请号：US12397948

申请日：2009-03-04

申请人： Kuo-Cheng Ching ,  Kuo-Chi Tu ,  Chun-Yao Chen

发明人： Kuo-Cheng Ching ,  Kuo-Chi Tu ,  Chun-Yao Chen

IPC分类号： H01L27/108 ,  H01L29/92 ,  H01L21/02

CPC分类号： H01L27/0805 ,  H01L27/0629 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91

摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer.

摘要翻译： 本公开提供了一种半导体器件，其包括半导体衬底，形成在半导体衬底中的隔离结构，在隔离结构上形成的导电层，以及形成在隔离结构上的金属 - 绝缘体 - 金属（MIM）电容器。 MIM电容器具有冠状形状，其包括顶部电极，第一底部电极和设置在顶部电极和第一底部电极之间的电介质，第一底部电极至少延伸到导电层的顶表面。

公开(公告)号：US20100187589A1

公开(公告)日：2010-07-29

申请号：US12753594

申请日：2010-04-02

申请人： Kuo-Chi TU

发明人： Kuo-Chi TU

IPC分类号： H01L27/108 ,  H01L21/02

CPC分类号： H01L28/60 ,  H01L27/10855

摘要： Devices and methods for preventing capacitor leakage caused by sharp tip. The formation of sharp tip is avoided by a thicker bottom electrode which fully fills a micro-trench that induces formation of the sharp tip. Alternatively, formation of the sharp tip can be avoided by recessing the contact plug to substantially eliminate the micro-trench

摘要翻译： 用于防止由尖端引起的电容器泄漏的装置和方法。 通过较厚的底部电极避免形成尖锐尖端，该底部电极完全填充引起锋利尖端形成的微沟槽。 或者，可以通过使接触插塞凹陷以基本上消除微沟槽来避免尖端尖端的形成

公开(公告)号：US20100109124A1

公开(公告)日：2010-05-06

申请号：US12683224

申请日：2010-01-06

申请人： Kuo-Chi TU

发明人： Kuo-Chi TU

IPC分类号： H01L29/92

CPC分类号： H01L28/86 ,  H01L27/10817 ,  H01L27/10852

摘要： A method of forming a metal-insulator-metal capacitor has the following steps. A stack dielectric structure is formed by alternately depositing a plurality of second dielectric layers and a plurality of third dielectric layers. A wet etch selectivity of the second dielectric layer relative to said third dielectric layer is of at least 5:1. An opening is formed in the stack dielectric structure, and then a wet etch process is employed to remove relatively-large portions of the second dielectric layers and relatively-small portions of the third dielectric layers to form a plurality of lateral recesses in the second dielectric layers along sidewalls of the opening. A bottom electrode layer is formed to extend along the serrate sidewalls, a capacitor dielectric layer is formed on the bottom electrode layer, and a top electrode layer is formed on the capacitor dielectric layer.

摘要翻译： 金属 - 绝缘体 - 金属电容器的形成方法如下。 通过交替地沉积多个第二电介质层和多个第三电介质层来形成堆叠电介质结构。 第二电介质层相对于所述第三电介质层的湿蚀刻选择性为至少5:1。 在堆叠电介质结构中形成开口，然后采用湿式蚀刻工艺来除去第二电介质层的相对大的部分和第三电介质层的相对较小的部分，以在第二电介质中形成多个横向凹槽 沿着开口的侧壁的层。 形成底电极层沿着锯齿状侧壁延伸，在底电极层上形成电容电介质层，在电容介电层上形成顶电极层。

公开(公告)号：US20100065944A1

公开(公告)日：2010-03-18

申请号：US12212096

申请日：2008-09-17

申请人： Kuo-Chi TU ,  Huey-Chi Chu ,  Kuo-Cheng Ching

发明人： Kuo-Chi TU ,  Huey-Chi Chu ,  Kuo-Cheng Ching

IPC分类号： H01L29/92

CPC分类号： H01L23/5223 ,  H01L27/0629 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes a circuit module having a plurality of active components coupled between a pair of supply nodes, and a capacitive decoupling module coupled to the circuit module. The capacitive decoupling module includes a plurality of metal-insulator-metal (MiM) capacitors coupled in series between the pair of supply nodes, wherein a voltage between the supply nodes is divided across the plurality of MiM capacitors, thereby reducing voltage stress on the capacitors.

摘要翻译： 集成电路包括具有耦合在一对电源节点之间的多个有源元件的电路模块和耦合到电路模块的电容去耦模块。 电容去耦模块包括串联耦合在一对电源节点之间的多个金属 - 绝缘体 - 金属（MiM）电容器，其中供电节点之间的电压在多个MiM电容器之间分开，从而减小电容器上的电压应力 。

公开(公告)号：US07329953B2

公开(公告)日：2008-02-12

申请号：US10696006

申请日：2003-10-29

申请人： Kuo-Chi Tu

发明人： Kuo-Chi Tu

IPC分类号： H01L31/0232 ,  H01L23/48 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L27/10852 ,  H01L23/485 ,  H01L27/10811 ,  H01L27/10894 ,  H01L27/10897

摘要： A method for fabricating an insulating layer having contact openings of varying depths for logic/DRAM circuits is achieved using a single mask and etch step. After forming stacked or trench capacitors, a planar insulating layer is formed. Contact openings are etched in the planar insulating layer to the substrate, and contact openings that extend over the edge of the stacked or trench capacitor top electrode, having an ARC, are etched using a novel mask design and a single etching step. This allows one to make contacts to the substrate without overetching while making low-resistance contacts to the sidewall of the capacitor top electrode. In the trench capacitor open areas are formed to facilitate making contact openings that extend over the top electrode. A series of contact openings that are skewed or elongated also improve the latitude in alignment tolerance.

摘要翻译： 使用单个掩模和蚀刻步骤来实现用于制造具有用于逻辑/ DRAM电路的不同深度的接触开口的绝缘层的方法。 在形成堆叠或沟槽电容器之后，形成平面绝缘层。 接触开口在平面绝缘层中蚀刻到基板上，并且使用新颖的掩模设计和单个蚀刻步骤蚀刻在具有ARC的堆叠或沟槽电容器顶部电极的边缘上延伸的接触开口。 这允许在对电容器顶部电极的侧壁进行低电阻接触的同时，不过度地进行与基板的接触。 在沟槽电容器中形成开放区域以便于形成在顶部电极上延伸的接触开口。 歪斜或伸长的一系列接触开口也提高了对准公差的纬度。

公开(公告)号：US07271083B2

公开(公告)日：2007-09-18

申请号：US10896491

申请日：2004-07-22

申请人： Kuo-Chi Tu ,  Kuo-Chyuan Tzeng ,  Chung-Yi Chen ,  C. Y. Shen ,  Chun-Yao Chen ,  Hsiang-Fan Lee

发明人： Kuo-Chi Tu ,  Kuo-Chyuan Tzeng ,  Chung-Yi Chen ,  C. Y. Shen ,  Chun-Yao Chen ,  Hsiang-Fan Lee

IPC分类号： H01L29/76

CPC分类号： H01L27/10861 ,  H01L27/10873

摘要： One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM capacitor embedded isolation structure.

摘要翻译： 与金属栅极工艺兼容的单晶体管RAM技术制造由与MIM电容器嵌入式隔离结构的顶部电极相同的金属材料形成的金属栅电极。 栅极电介质层由与MIM电容器嵌入式隔离结构的电容器电介质相同的高k电介质材料形成。