公开(公告)号：US08748284B2

公开(公告)日：2014-06-10

申请号：US13209195

申请日：2011-08-12

申请人： Kuo-Chyuan Tzeng ,  Kuo-Chi Tu ,  Chen-Jong Wang ,  Hsiang-Fan Lee

发明人： Kuo-Chyuan Tzeng ,  Kuo-Chi Tu ,  Chen-Jong Wang ,  Hsiang-Fan Lee

IPC分类号： H01L21/20

CPC分类号： H01L28/40 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/49822 ,  H01L23/5223 ,  H01L24/83 ,  H01L27/06 ,  H01L27/0805 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

摘要： Decoupling metal-insulator-metal (MIM) capacitor designs for interposers and methods of manufacture thereof are disclosed. In one embodiment, a method of forming a decoupling capacitor includes providing a packaging device, and forming a decoupling MIM capacitor in at least two metallization layers of the packaging device.

摘要翻译： 公开了用于插入件的去耦金属绝缘体金属（MIM）电容器设计及其制造方法。 在一个实施例中，形成去耦电容器的方法包括提供封装装置，以及在包装装置的至少两个金属化层中形成去耦MIM电容器。

公开(公告)号：US08716100B2

公开(公告)日：2014-05-06

申请号：US13212922

申请日：2011-08-18

申请人： Kuo-Chyuan Tzeng ,  Luan C. Tran ,  Chen-Jong Wang ,  Kuo-Chi Tu ,  Hsiang-Fan Lee

发明人： Kuo-Chyuan Tzeng ,  Luan C. Tran ,  Chen-Jong Wang ,  Kuo-Chi Tu ,  Hsiang-Fan Lee

IPC分类号： H01L21/20

CPC分类号： H01L28/86 ,  H01L23/5223 ,  H01L28/40 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of MIM capacitors may be embedded into a thick IMD layer with enough thickness (e.g., 10 KŘ30 KÅ) to get high capacitance, which may be on top of a thinner IMD layer. MIM capacitors may be formed among three adjacent metal layers which have two thick IMD layers separating the three adjacent metal layers. Materials such as TaN or TiN are used as bottom/top electrodes & Cu barrier. The metal layer above the thick IMD layer may act as the top electrode connection. The metal layer under the thick IMD layer may act as the bottom electrode connection. The capacitor may be of different shapes such as cylindrical shape, or a concave shape. Many kinds of materials (Si3N4, ZrO2, HfO2, BST . . . etc) can be used as the dielectric material. The MIM capacitors are formed by one or two extra masks while forming other non-capacitor logic of the circuit.

摘要翻译： MIM电容器的实施例可以嵌入到具有足够厚度（例如，10K〜30K）的厚IMD层中以获得高电容，其可以在更薄的IMD层之上。 可以在三个相邻的金属层之间形成MIM电容器，这两个相邻的金属层具有两个分开三个相邻金属层的厚的IMD层。 诸如TaN或TiN的材料用作底部/顶部电极和Cu屏障。 厚IMD层上方的金属层可以用作顶部电极连接。 厚IMD层下面的金属层可以用作底部电极连接。 电容器可以是不同的形状，例如圆柱形或凹形。 可以使用多种材料（Si3N4，ZrO2，HfO2，BST等）作为介电材料。 MIM电容器由一个或两个额外的掩模形成，同时形成电路的其他非电容器逻辑。

公开(公告)号：US20130043560A1

公开(公告)日：2013-02-21

申请号：US13212922

申请日：2011-08-18

申请人： Kuo-Chyuan Tzeng ,  Luan C. Tran ,  Chen-Jong Wang ,  Kuo-Chi Tu ,  Hsiang-Fan Lee

发明人： Kuo-Chyuan Tzeng ,  Luan C. Tran ,  Chen-Jong Wang ,  Kuo-Chi Tu ,  Hsiang-Fan Lee

IPC分类号： H01L27/06 ,  H01L21/02

CPC分类号： H01L28/86 ,  H01L23/5223 ,  H01L28/40 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of MIM capacitors may be embedded into a thick IMD layer with enough thickness (e.g., 10 KŘ30 KÅ) to get high capacitance, which may be on top of a thinner IMD layer. MIM capacitors may be formed among three adjacent metal layers which have two thick IMD layers separating the three adjacent metal layers. Materials such as TaN or TiN are used as bottom/top electrodes & Cu barrier. The metal layer above the thick IMD layer may act as the top electrode connection. The metal layer under the thick IMD layer may act as the bottom electrode connection. The capacitor may be of different shapes such as cylindrical shape, or a concave shape. Many kinds of materials (Si3N4, ZrO2, HfO2, BST . . . etc) can be used as the dielectric material. The MIM capacitors are formed by one or two extra masks while forming other non-capacitor logic of the circuit.

摘要翻译： MIM电容器的实施例可以嵌入到具有足够厚度（例如，10K〜30K）的厚IMD层中以获得高电容，其可以在更薄的IMD层之上。 可以在三个相邻的金属层之间形成MIM电容器，这两个相邻的金属层具有两个分开三个相邻金属层的厚的IMD层。 诸如TaN或TiN的材料用作底部/顶部电极和Cu屏障。 厚IMD层上方的金属层可以用作顶部电极连接。 厚IMD层下面的金属层可以用作底部电极连接。 电容器可以是不同的形状，例如圆柱形或凹形。 可以使用多种材料（Si3N4，ZrO2，HfO2，BST等）作为介电材料。 MIM电容器由一个或两个额外的掩模形成，同时形成电路的其他非电容器逻辑。

公开(公告)号：US20120091559A1

公开(公告)日：2012-04-19

申请号：US13267424

申请日：2011-10-06

申请人： Kuo-Chi Tu ,  Wen-Chuan Chiang ,  Chen-Jong Wang

发明人： Kuo-Chi Tu ,  Wen-Chuan Chiang ,  Chen-Jong Wang

IPC分类号： H01L21/02 ,  H01L29/92

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1116 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system-on-chip (SOC) device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or different thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, a radio frequency region, a dynamic random access memory region, and so forth.

摘要翻译： 片上系统（SOC）装置包括第一区域中的第一电容器，第二区域中的第二电容器，以及可以在第三区域中包括第三电容器，以及附加区域中的任何附加数量的电容器。 电容器可以具有不同的形状和尺寸。 区域可以包括多于一个的电容器。 区域中的每个电容器具有顶部电极，底部电极和电容器绝缘体。 所有电容器的顶部电极以公共工艺形成，而所有电容器的底部电极形成在共同的工艺中。 电容绝缘体可以具有不同数量的子层，形成不同的材料或不同的厚度。 电容器可以形成在层间电介质层中或在金属间介电层中。 这些区域可以是混合信号区域，模拟区域，射频区域，动态随机存取存储区域等。

公开(公告)号：US07851861B2

公开(公告)日：2010-12-14

申请号：US11655855

申请日：2007-01-22

申请人： Kuo-Chi Tu

发明人： Kuo-Chi Tu

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01G2/00

CPC分类号： H01G4/002 ,  H01G4/40 ,  H01G13/00 ,  H01G17/00 ,  H01L21/823828 ,  H01L27/0629 ,  H01L27/10852 ,  H01L28/60 ,  H01L29/66545

摘要： A device includes an embedded MIM capacitor and a transistor formed in parallel with reduced processing steps and improved device performance in different regions of a substrate. The embedded MIM capacitor has a bottom electrode, an insulator layer, a dielectric film, and a top electrode. The substrate has an insulator region. The bottom electrode, having a first conductor, overlies the insulator region. The insulator layer overlies the substrate and the bottom electrode. The insulator layer has an opening connecting parts of the bottom electrode. The dielectric film lines the opening, and is disposed directly on the bottom electrode and sidewalls of the opening. The top electrode, having a second conductor, overlies the dielectric film in the opening. The dielectric film lines sidewalls and bottom of the top electrode.

摘要翻译： 一种器件包括一个嵌入式MIM电容器和一个并联形成的晶体管，并减少了处理步骤，并提高了器件在衬底的不同区域的性能。 嵌入式MIM电容器具有底部电极，绝缘体层，电介质膜和顶部电极。 衬底具有绝缘体区域。 具有第一导体的底部电极覆盖绝缘体区域。 绝缘体层覆盖在基底和底部电极上。 绝缘体层具有连接底部电极的部分的开口。 电介质膜对开口进行排列，并直接设置在底部电极和开口的侧壁上。 具有第二导体的顶部电极覆盖开口中的电介质膜。 电介质膜线路顶部电极的侧壁和底部。

公开(公告)号：US20080145997A1

公开(公告)日：2008-06-19

申请号：US11640208

申请日：2006-12-18

申请人： Kuo-Chi Tu

发明人： Kuo-Chi Tu

IPC分类号： H01L21/20

CPC分类号： H01L28/86 ,  H01L27/10817 ,  H01L27/10852

摘要： A method of forming a metal-insulator-metal capacitor has the following steps. A stack dielectric structure is formed by alternately depositing a plurality of second dielectric layers and a plurality of third dielectric layers. A wet etch selectivity of the second dielectric layer relative to said third dielectric layer is of at least 5:1. An opening is formed in the stack dielectric structure, and then a wet etch process is employed to remove relatively-large portions of the second dielectric layers and relatively-small portions of the third dielectric layers to form a plurality of lateral recesses in the second dielectric layers along sidewalls of the opening. A bottom electrode layer is formed to extend along the serrate sidewalls, a capacitor dielectric layer is formed on the bottom electrode layer, and a top electrode layer is formed on the capacitor dielectric layer.

摘要翻译： 金属 - 绝缘体 - 金属电容器的形成方法如下。 通过交替地沉积多个第二电介质层和多个第三电介质层来形成堆叠电介质结构。 第二电介质层相对于所述第三电介质层的湿蚀刻选择性为至少5:1。 在堆叠电介质结构中形成开口，然后采用湿式蚀刻工艺来除去第二电介质层的相对大的部分和第三电介质层的相对小的部分，以在第二电介质中形成多个横向凹槽 沿着开口的侧壁的层。 形成底电极层沿着锯齿状侧壁延伸，在底电极层上形成电容电介质层，在电容介电层上形成顶电极层。

公开(公告)号：US20070200162A1

公开(公告)日：2007-08-30

申请号：US11361330

申请日：2006-02-24

申请人： Kuo-Chi Tu ,  Chun-Yao Chen ,  Yi-Ching Lin

发明人： Kuo-Chi Tu ,  Chun-Yao Chen ,  Yi-Ching Lin

IPC分类号： H01L29/76

CPC分类号： H01L28/40 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/56

摘要： A memory device having improved sensing speed and reliability and a method of forming the same are provided. The memory device includes a first dielectric layer having a low k value over a semiconductor substrate, a second dielectric layer having a second k value over the first dielectric layer, and a capacitor formed in the second dielectric layer wherein the capacitor comprises a cup region at least partially filled by the third dielectric layer. The memory device further includes a third dielectric layer over the second dielectric layer and a bitline over the third dielectric layer. The bitline is electrically coupled to the capacitor. A void having great dimensions is preferably formed in the cup region of the capacitor.

摘要翻译： 提供了具有改进的感测速度和可靠性的记忆装置及其形成方法。 存储器件包括在半导体衬底上具有低k值的第一电介质层，在第一介电层上具有第二k值的第二电介质层和形成在第二电介质层中的电容器，其中电容器包括位于 最少部分地被第三介电层填充。 存储器件还包括第二电介质层上的第三电介质层和第三电介质层上的位线。 位线电耦合到电容器。 优选地，在电容器的杯区域中形成具有大尺寸的空隙。

公开(公告)号：US20070063251A1

公开(公告)日：2007-03-22

申请号：US11233344

申请日：2005-09-22

申请人： Kuo-Chi Tu ,  Hsiang-Fan Lee

发明人： Kuo-Chi Tu ,  Hsiang-Fan Lee

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11529 ,  Y10S257/904

摘要： A semiconductor product and a method for fabricating the semiconductor product employ a semiconductor substrate. The semiconductor substrate has a logic region having a logic device formed therein, a non-volatile memory region having a non-volatile memory device formed therein and a volatile memory device having a volatile memory device formed therein. Gate electrode and capacitor plate layer components within each of the devices may be formed simultaneously incident to patterning of a single blanket gate electrode material layer

摘要翻译： 半导体产品和半导体产品的制造方法采用半导体衬底。 半导体衬底具有其中形成有逻辑器件的逻辑区域，其中形成有非易失性存储器件的非易失性存储器区域和其中形成有易失性存储器件的易失性存储器件。 可以在每个器件内的栅电极和电容器板层组件同时入射到单个覆盖栅极电极材料层的图案化

公开(公告)号：US07163853B2

公开(公告)日：2007-01-16

申请号：US11054448

申请日：2005-02-09

申请人： Kuo-Chi Tu

发明人： Kuo-Chi Tu

IPC分类号： H01L21/338

CPC分类号： H01L27/10873 ,  H01L21/28079 ,  H01L27/10805 ,  H01L27/1085 ,  H01L28/60 ,  H01L29/495 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/926

摘要： A method of manufacturing a capacitor and a metal gate on a semiconductor device comprises forming a dummy gate on a substrate, forming a trench layer on the substrate and adjacent the dummy gate, forming a capacitor trench in the trench layer, forming a bottom electrode layer in the capacitor trench, removing the dummy gate to provide a gate trench, forming a dielectric layer in the capacitor trench and the gate trench, and forming a metal layer over the dielectric layer in the capacitor trench and the gate trench.

摘要翻译： 在半导体器件上制造电容器和金属栅极的方法包括在衬底上形成虚拟栅极，在衬底上形成沟槽层并与伪栅极相邻，在沟槽层中形成电容器沟槽，形成底部电极层 在电容器沟槽中，去除伪栅极以提供栅极沟槽，在电容器沟槽和栅极沟槽中形成介电层，并在电容器沟槽和栅极沟槽中的介电层上形成金属层。

公开(公告)号：US07019348B2

公开(公告)日：2006-03-28

申请号：US10789527

申请日：2004-02-26

申请人： Kuo-Chi Tu

发明人： Kuo-Chi Tu

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L21/76232 ,  H01L21/76229

摘要： An embedded semiconductor product employs a first isolation trench and first isolation region formed therein adjoining a logic cell active region of a semiconductor substrate. The embedded semiconductor product also employs a second isolation trench and second isolation region formed therein adjoining a memory cell active region of the semiconductor substrate. The second isolation trench is deeper than the first isolation trench such that a storage capacitor whose capacitor plate is embedded at least in part within the second isolation region may be formed with enhanced capacitance.

摘要翻译： 嵌入式半导体产品采用第一隔离沟槽和形成在其中的与半导体衬底的逻辑单元有源区相邻的第一隔离区。 嵌入式半导体产品还采用与半导体衬底的存储单元有源区相邻形成的第二隔离沟道和第二隔离区。 第二隔离沟槽比第一隔离沟槽更深，使得其电容器板至少部分地嵌入在第二隔离区域内的存储电容器可以形成为增强的电容。