公开(公告)号：US5631185A

公开(公告)日：1997-05-20

申请号：US499327

申请日：1995-07-07

申请人： Young-pil Kim ,  Jong-bok Kim ,  Kweon-jae Lee

发明人： Young-pil Kim ,  Jong-bok Kim ,  Kweon-jae Lee

IPC分类号： H01L27/08 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/87

摘要： A method for manufacturing a capacitor of a semiconductor memory device is provided. A first insulating layer and a second insulating layer are formed in sequence on a semiconductor substrate on which a transistor including a source region, a drain region and a gate electrode, and a buried bit-line surrounded by insulating layer are formed. Then, a contact hole is formed by sequentially etching the layers stacked on the source region, by which the source region of the transistor is exposed, and a spacer made of an insulating substance is formed inside the contact hole, and a first conductive layer is formed on the whole surface of the resultant. Next, the first conductive layer and second insulating layer are etched, and a second conductive layer is formed on the whole surface of the resultant, and a storage electrode is formed by etching the second conductive layer using the first conductive layer as a mask. According to the method, the step for forming the contact hole is very simple and less photolithography steps are required since the first conductive layer is used as a mask for etching the second conductive layer, thereby simplifying the manufacturing process.

摘要翻译： 提供一种制造半导体存储器件的电容器的方法。 在半导体衬底上依次形成第一绝缘层和第二绝缘层，在半导体衬底上形成包括源极区，漏极区和栅电极的晶体管，以及由绝缘层包围的掩埋位线。 然后，通过依次蚀刻堆叠在源区域上的层，形成晶体管的源极区域而暴露的层，并且在接触孔内部形成由绝缘物质构成的间隔物，并且第一导电层为 形成在所得物的整个表面上。 接下来，蚀刻第一导电层和第二绝缘层，并且在所得的整个表面上形成第二导电层，并且通过使用第一导电层作为掩模蚀刻第二导电层来形成存储电极。 根据该方法，用于形成接触孔的步骤非常简单，因为使用第一导电层作为用于蚀刻第二导电层的掩模，因此简化了制造工艺，因此需要较少的光刻步骤。

公开(公告)号：US06580175B1

公开(公告)日：2003-06-17

申请号：US09710833

申请日：2000-11-14

申请人： Kweon-Jae Lee

发明人： Kweon-Jae Lee

IPC分类号： H01L2941

CPC分类号： H01L27/10855 ,  H01L23/485 ,  H01L27/0207 ,  H01L27/10814 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention discloses a layout in a semiconductor device having conductive layers electrically connected to conductive regions via contact holes beneath the conductive layers. Each of the conductive layers has a layout with different widths at opposite longitudinal ends thereof, respectively, thereby being capable of achieving an improvement in the alignment margin between the conductive layer and the contact hole within a given memory cell area. Where the layout is applied to capacitors, it is possible to avoid the formation of inferior storage electrodes over regions where contact holes are formed.

摘要翻译： 本发明公开了一种半导体器件中的布局，其具有通过导电层下面的接触孔与导电区域电连接的导电层。 每个导电层在其相对的纵向端部具有不同宽度的布局，从而能够实现给定存储单元区域内的导电层和接触孔之间的对准边缘的改进。 在将布局应用于电容器的情况下，可以避免在形成接触孔的区域上形成劣质存储电极。

公开(公告)号：US06486556B1

公开(公告)日：2002-11-26

申请号：US09671213

申请日：2000-09-28

申请人： Kweon-Jae Lee ,  Weon-Chul Hong

发明人： Kweon-Jae Lee ,  Weon-Chul Hong

IPC分类号： H01L2352

CPC分类号： H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A layout structure of the interconnection layers of a semiconductor device includes a plurality of conducting lines extending adjacent one another, and at least one rectangular cut-out formed in a side of each of the conducting lines, wherein a width of gap between adjacent ones of the plurality of conducting lines is increased at each rectangular cut-out. The rectangular cut-out serves to increase the space between adjacent conducting lines so as to secure a proper gap there between upon deposition of a passivation layer.

摘要翻译： 半导体器件的互连层的布局结构包括彼此相邻延伸的多条导线以及形成在每条导线的一侧的至少一个矩形切口，其中相邻的导电线之间的间隙宽度 多个导线在每个矩形切口处增加。 矩形切口用于增加相邻导线之间的空间，以便在沉积钝化层之间确保其间的适当间隙。