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23 条记录 (耗时 0.013 秒)

    Inductor for semiconductor device and method for making the same
    3.
    发明授权
    Inductor for semiconductor device and method for making the same 失效
    半导体器件用电感器及其制造方法

    公开(公告)号：US06303971B1

    公开(公告)日：2001-10-16

    申请号：US08974371

    申请日：1997-11-19

    申请人： Tae-Pok Rhee

    发明人： Tae-Pok Rhee

    IPC分类号： H01L2941

    CPC分类号： H01L28/10 ,  H01F17/0033 ,  H01L27/08

    摘要： An inductor for a semiconductor device is formed within a groove in an insulating layer on a semiconductor substrate. A number of lower conductive lines are formed across the groove. A cylindrical insulator is formed over the lower conductive lines and aligned with the groove. Upper conductive lines are formed over the cylindrical insulator. The upper and lower conductive lines are slanted lengthwise along the groove in opposite directions to form a spiral coil having a circular cross-section, thereby preventing abrupt changes in the magnetic field. The ends of upper conductive lines contact the ends of the lower conductive lines so that the thickness of the coil is controlled by the thickness of the cylindrical insulator, thereby allowing the self-inductance to be increased and the positional density of the conductive lines to be freely controlled.

    摘要翻译： 用于半导体器件的电感器形成在半导体衬底上的绝缘层的沟槽内。 多个下导电线跨越沟槽形成。 在下导电线上形成圆柱形绝缘体，并与凹槽对准。 上导电线形成在圆柱形绝缘体上。 上下导线沿相反方向的槽沿纵向倾斜以形成具有圆形横截面的螺旋线圈，从而防止磁场的突然变化。 上导电线的端部接触下导电线的端部，使得线圈的厚度由圆柱形绝缘体的厚度控制，从而允许增加自感并且使导线的位置密度为 自由控制。

    Semiconductor device with bipolar and J-FET transistors
    4.
    发明授权
    Semiconductor device with bipolar and J-FET transistors 有权
    具有双极和J-FET晶体管的半导体器件

    公开(公告)号：US06278143B1

    公开(公告)日：2001-08-21

    申请号：US09145431

    申请日：1998-09-01

    申请人： Hirokazu Ejiri

    发明人： Hirokazu Ejiri

    IPC分类号： H01L2941

    CPC分类号： H01L21/8248 ,  H01L27/0623

    摘要： In a semiconductor device by a complex-type bipolar transistor device in which a junction-type field effect transistor is connected to a bipolar transistor, to make it possible to ensure a good and stable characteristic of the bipolar transistor without incurring a larger area in the junction-type field effect transistor J-FET. In a semiconductor device having a bipolar transistor (TR) and a junction-type field effect transistor (J-FET), in which a collector of the bipolar transistor and a source of the junction-type field effect transistor are connected, a gate region (14) of the junction-type field effect transistor, a gate contact conductive layer 17G, and a drain contact conductive layer 18D for a drain region are formed of conductive layers which are formed as respectively different layers with a same conductive material or mutually different materials and an arrangement surface of an edge portion 17G1 on the drain side of the gate contact conductive layer is positioned below an arrangement surface of an edge portion 18D1 on the gate side of the drain contact conductive layer.

    摘要翻译： 在其中结型场效应晶体管连接到双极晶体管的复合型双极晶体管器件的半导体器件中，为了确保双极型晶体管的良好且稳定的特性而不会产生更大的面积， 结型场效应晶体管J-FET。在具有双极型晶体管（TR）和结型场效应晶体管（J-FET）的半导体器件中，其中双极晶体管的集电极和结型场效应晶体管的源极， 连接型场效应晶体管，接合型场效应晶体管的栅极区域（14），栅极接触导电层17G和漏极区域的漏极接触导电层18D由分别形成的导电层形成 具有相同导电材料或相互不同的材料的不同层和栅极接触导电层的漏极侧上的边缘部分17G1的布置表面位于ar 在漏极接触导电层的栅极侧的边缘部分18D1的尺寸表面。

    Semiconductor device having patterned metal layer over a polysilicon line and method of fabrication thereof
    5.
    发明授权
    Semiconductor device having patterned metal layer over a polysilicon line and method of fabrication thereof 有权
    具有多晶硅线上的图案化金属层的半导体器件及其制造方法

    公开(公告)号：US06249032B1

    公开(公告)日：2001-06-19

    申请号：US09165051

    申请日：1998-10-01

    申请人： Homi E. Nariman ,  H. Jim Fulford ,  Charles E. May

    发明人： Homi E. Nariman ,  H. Jim Fulford ,  Charles E. May

    IPC分类号： H01L2941

    CPC分类号： H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device and fabrication process are provided in which a patterned metal layer is formed over a polysilicon line. The polysilicon line is disposed on a substrate and may, for example, be a gate electrode. A dielectric layer is disposed adjacent the polysilicon line and the patterned metal layer is formed over the polysilicon line. The device may further include a second polysilicon line, such as a gate electrode, and the patterned metal layer may extend over the top of the second polysilicon line and interconnect the two polysilicon lines. A contact for the polysilicon line is coupled to the patterned metal layer. The use of a patterned metal line may provide a larger footprint for the contact then the underlying polysilicon line(s) and may decrease the sheet resistance to the polysilicon line(s).

    摘要翻译： 提供半导体器件和制造工艺，其中在多晶硅线上形成图案化的金属层。 多晶硅线路设置在基板上，并且可以例如是栅电极。 介电层设置在多晶硅线附近并且在多晶硅线上形成图案化的金属层。 该器件还可以包括第二多晶硅线，例如栅电极，并且图案化的金属层可以在第二多晶硅线的顶部上延伸并互连两个多晶硅线。 用于多晶硅线的触点耦合到图案化的金属层。 使用图案化金属线可以为接触提供更大的覆盖，然后是下面的多晶硅线，并且可以降低对多晶硅线的薄层电阻。

    Switching circuit with improved signal blocking effect in off mode
    6.
    发明授权
    Switching circuit with improved signal blocking effect in off mode 失效
    开关电路在关断模式下具有改善的信号阻塞效应

    公开(公告)号：US06800935B2

    公开(公告)日：2004-10-05

    申请号：US10256692

    申请日：2002-09-27

    申请人： Toshiharu Yoneda

    发明人： Toshiharu Yoneda

    IPC分类号： H01L2941

    CPC分类号： H05K1/0243 ,  H05K3/3421 ,  H05K2201/09481 ,  H05K2201/10174 ,  H05K2201/10969

    摘要： A switching circuit includes an insulating substrate including two signal transmission lines; a switching diode mounted, in series between the two signal transmission lines, on the insulating substrate, wherein an anode terminal and a cathode terminal are connected to the two signal transmission lines, and the switching diode is turned on or off; and a conductive pattern formed, below the switching diode, on a mounting face of the insulating substrate on which the switching diode is mounted, wherein the conductive pattern is grounded. There are stray capacitances between the anode terminal and the conductive pattern and between the cathode terminal and the conductive pattern.

    摘要翻译： 开关电路包括：绝缘基板，包括两条信号传输线; 串联在两个信号传输线之间的绝缘基板上的开关二极管，其中阳极端子和阴极端子连接到两个信号传输线，并且开关二极管导通或关断; 以及在开关二极管的下方形成在其上安装有开关二极管的绝缘基板的安装面上的导电图案，其中导电图案接地。 在阳极端子和导电图案之间以及阴极端子和导电图案之间存在杂散电容。

    Semiconductor layout structure for a conductive layer and contact hole
    7.
    发明授权
    Semiconductor layout structure for a conductive layer and contact hole 有权
    用于导电层和接触孔的半导体布局结构

    公开(公告)号：US06580175B1

    公开(公告)日：2003-06-17

    申请号：US09710833

    申请日：2000-11-14

    申请人： Kweon-Jae Lee

    发明人： Kweon-Jae Lee

    IPC分类号： H01L2941

    CPC分类号： H01L27/10855 ,  H01L23/485 ,  H01L27/0207 ,  H01L27/10814 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention discloses a layout in a semiconductor device having conductive layers electrically connected to conductive regions via contact holes beneath the conductive layers. Each of the conductive layers has a layout with different widths at opposite longitudinal ends thereof, respectively, thereby being capable of achieving an improvement in the alignment margin between the conductive layer and the contact hole within a given memory cell area. Where the layout is applied to capacitors, it is possible to avoid the formation of inferior storage electrodes over regions where contact holes are formed.

    摘要翻译： 本发明公开了一种半导体器件中的布局，其具有通过导电层下面的接触孔与导电区域电连接的导电层。 每个导电层在其相对的纵向端部具有不同宽度的布局，从而能够实现给定存储单元区域内的导电层和接触孔之间的对准边缘的改进。 在将布局应用于电容器的情况下，可以避免在形成接触孔的区域上形成劣质存储电极。

    SOI FET body contact structure
    10.
    发明授权
    SOI FET body contact structure 有权
    SOI FET体接触结构

    公开(公告)号：US06177708B1

    公开(公告)日：2001-01-23

    申请号：US09324324

    申请日：1999-06-02

    申请人： Jente B. Kuang ,  John P. Pennings ,  George E. Smith, III ,  Michael H. Wood

    发明人： Jente B. Kuang ,  John P. Pennings ,  George E. Smith, III ,  Michael H. Wood

    IPC分类号： H01L2941

    CPC分类号： H01L27/1203 ,  H01L29/42384 ,  H01L29/78606 ,  H01L29/78618

    摘要： A self-aligned SOI FET device with an “L” shaped gate structure allows an integral diode junction to be formed between the source and the body of the device. Two devices with this gate geometry can be advantageously placed side-by-side in a single rx opening that could accommodate but a single device with a “T” shaped gate structure. The devices in accordance with the teachings of this invention can be easily formed using standard prior art SOI processing steps. An aspect of this invention includes the use of these novel SOI devices with their body and source connected together in circuit applications, such as memory cell sense amplifiers, where high speed operation commends the use of SOI technology, but physical space considerations have limited their application.

    摘要翻译： 具有“L”形栅极结构的自对准SOI FET器件允许在器件的源极和主体之间形成整体二极管结。 具有该栅极几何形状的两个器件可以有利地并排布置在可容纳但具有“T”形栅极结构的单个器件的单个rx开口中。 根据本发明的教导的器件可以使用标准的现有技术的SOI处理步骤容易地形成。 本发明的一个方面包括使用这些新颖的SOI器件，其主体和源极在诸如存储器单元读出放大器的电路应用中连接在一起，其中高速操作表示使用SOI技术，但是物理空间考虑限制了它们的应用 。