公开(公告)号：US10198333B2

公开(公告)日：2019-02-05

申请号：US13997182

申请日：2010-12-23

申请人： Mark B. Trobough ,  Keshavan K. Tiruvallur ,  Chinna B. Prudvi ,  Christian E. Iovin ,  David W. Grawrock ,  Jay J. Nejedlo ,  Ashok N. Kabadi ,  Travis K. Goff ,  Evan J. Halprin ,  Kapila B. Udawatta ,  Jiun Long Foo ,  Wee Hoo Cheah ,  Vui Yong Liew ,  Selvakumar Raja Gopal ,  Yuen Tat Lee ,  Samie B. Samaan ,  Kip C. Killpack ,  Neil Dobler ,  Nagib Z. Hakim ,  Brian Meyer ,  William H. Penner ,  John L. Baudrexl ,  Russell J. Wunderlich ,  James J. Grealish ,  Kyle Markley ,  Timothy S. Storey ,  Loren J. McConnell ,  Lyle E. Cool ,  Mukesh Kataria ,  Rahima K. Mohammed ,  Tieyu Zheng ,  Yi Amy Xia ,  Ridvan A. Sahan ,  Arun R. Ramadorai ,  Priyadarsan Patra ,  Edwin E. Parks ,  Abhijit Davare ,  Padmakumar Gopal ,  Bruce Querbach ,  Hermann W. Gartler ,  Keith Drescher ,  Sanjay S. Salem ,  David C. Florey

发明人： Mark B. Trobough ,  Keshavan K. Tiruvallur ,  Chinna B. Prudvi ,  Christian E. Iovin ,  David W. Grawrock ,  Jay J. Nejedlo ,  Ashok N. Kabadi ,  Travis K. Goff ,  Evan J. Halprin ,  Kapila B. Udawatta ,  Jiun Long Foo ,  Wee Hoo Cheah ,  Vui Yong Liew ,  Selvakumar Raja Gopal ,  Yuen Tat Lee ,  Samie B. Samaan ,  Kip C. Killpack ,  Neil Dobler ,  Nagib Z. Hakim ,  Brian Meyer ,  William H. Penner ,  John L. Baudrexl ,  Russell J. Wunderlich ,  James J. Grealish ,  Kyle Markley ,  Timothy S. Storey ,  Loren J. McConnell ,  Lyle E. Cool ,  Mukesh Kataria ,  Rahima K. Mohammed ,  Tieyu Zheng ,  Yi Amy Xia ,  Ridvan A. Sahan ,  Arun R. Ramadorai ,  Priyadarsan Patra ,  Edwin E. Parks ,  Abhijit Davare ,  Padmakumar Gopal ,  Bruce Querbach ,  Hermann W. Gartler ,  Keith Drescher ,  Sanjay S. Salem ,  David C. Florey

IPC分类号： G06F11/273 ,  G06F11/267

摘要： An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

公开(公告)号：US20150127983A1

公开(公告)日：2015-05-07

申请号：US13997182

申请日：2010-12-23

申请人： Mark B. Trobough ,  Keshavan K. Tiruvallur ,  Chinna B. Prudvi ,  Christian E. Iovin ,  David W. Grawrock ,  Jay J. Nejedlo ,  Ashok N. Kabadi ,  Travis K. Goff ,  Evan J. Halprin ,  Kapila B. Udawatta ,  Jiun Long Foo ,  Wee Hoo Cheah ,  Vui Yong Liew ,  Selvakumar Raja Gopal ,  Yuen Tat Lee ,  Samie B. Samaan ,  Kip C. Killpack ,  Neil Dobler ,  Nagib Z. Hakim ,  Briar Meyer ,  William H. Penner ,  John L. Baudrexl ,  Russell J. Wunderlich ,  James J. Grealish ,  Kyle Markley ,  Timothy S. Storey ,  Loren J. McConnell ,  Lyle E. Cool ,  Mukesh Kataria ,  Rahima K. Mohammed ,  Tieyu Zheng ,  Yi Amy Xia ,  Ridvan A. Sahan ,  Arun R. Ramadorai ,  Priyadarsan Patra ,  Edwin E. Parks ,  Abhijit Davare ,  Padmakumar Gopal ,  Bruce Querbach ,  Hermann W. Gartler ,  Keith Drescher ,  Sanjay S. Salem ,  David C. Florey

发明人： Mark B. Trobough ,  Keshavan K. Tiruvallur ,  Chinna B. Prudvi ,  Christian E. Iovin ,  David W. Grawrock ,  Jay J. Nejedlo ,  Ashok N. Kabadi ,  Travis K. Goff ,  Evan J. Halprin ,  Kapila B. Udawatta ,  Jiun Long Foo ,  Wee Hoo Cheah ,  Vui Yong Liew ,  Selvakumar Raja Gopal ,  Yuen Tat Lee ,  Samie B. Samaan ,  Kip C. Killpack ,  Neil Dobler ,  Nagib Z. Hakim ,  Briar Meyer ,  William H. Penner ,  John L. Baudrexl ,  Russell J. Wunderlich ,  James J. Grealish ,  Kyle Markley ,  Timothy S. Storey ,  Loren J. McConnell ,  Lyle E. Cool ,  Mukesh Kataria ,  Rahima K. Mohammed ,  Tieyu Zheng ,  Yi Amy Xia ,  Ridvan A. Sahan ,  Arun R. Ramadorai ,  Priyadarsan Patra ,  Edwin E. Parks ,  Abhijit Davare ,  Padmakumar Gopal ,  Bruce Querbach ,  Hermann W. Gartler ,  Keith Drescher ,  Sanjay S. Salem ,  David C. Florey

IPC分类号： G06F11/273

CPC分类号： G06F11/2733 ,  G06F11/267

摘要： An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

摘要翻译： 这里描述了一种用于提供测试，验证和调试架构的装置和方法。 在目标或基础级别，硬件（测试设计或DFx）被设计并集成在硅部件中。 控制器可以提供对这种钩子的抽象访问，例如通过抽象层来抽象硬件DFx的低级细节。 此外，通过接口（如API）的抽象层向更高级的软件/表示层提供服务，例程和数据结构，这些层能够收集测试数据，以便对被测单元/平台进行验证和调试。 此外，该架构可能提供对测试架构的分层（多级）安全访问。 此外，可以通过使用统一的双向测试访问端口来简化对平台的测试架构的物理访问，同时还可能允许远程访问执行被测部件/平台的远程测试和脱离。 本质上描述了一个完整的测试架构栈，用于电子部件，设备和平台的测试，验证和调试。

公开(公告)号：US20070245210A1

公开(公告)日：2007-10-18

申请号：US11395888

申请日：2006-03-31

申请人： Kyle Markley

发明人： Kyle Markley

IPC分类号： H03M13/00

CPC分类号： H04L43/50 ,  H04L69/03

摘要： A mechanism to obtain a quiescence state for a component coupled to a bidirectional communications interface is obtained. A transition to quiescence may be may by activating a first defeature in the component to cause messages received over a communication bus coupled between the component and another component to be ignored, and activating a second defeature in the component to prevent messages from being sent over the communication bus by the component. Operations may then be performed on the component while the defeatures are activated.

摘要翻译： 获得用于获得耦合到双向通信接口的部件的静止状态的机制。 通过激活组件中的第一个失败，可以通过激活在组件和另一个组件之间耦合的通信总线接收到的消息被忽略，并激活组件中的第二个失败，以防止消息被发送 通信总线由组件。 然后可以在启动失败时对组件执行操作。

公开(公告)号：US07596724B2

公开(公告)日：2009-09-29

申请号：US11395888

申请日：2006-03-31

申请人： Kyle Markley

发明人： Kyle Markley

IPC分类号： G06F11/00

CPC分类号： H04L43/50 ,  H04L69/03

摘要： A mechanism to obtain a quiescence state for a component coupled to a bidirectional communications interface is obtained. A transition to quiescence may be may by activating a first defeature in the component to cause messages received over a communication bus coupled between the component and another component to be ignored, and activating a second defeature in the component to prevent messages from being sent over the communication bus by the component. Operations may then be performed on the component while the defeatures are activated.

摘要翻译： 获得用于获得耦合到双向通信接口的部件的静止状态的机制。 通过激活组件中的第一个失败，可以通过激活在组件和另一个组件之间耦合的通信总线接收到的消息被忽略，并激活组件中的第二个失败，以防止消息被发送 通信总线由组件。 然后可以在启动失败时对组件执行操作。