公开(公告)号：US20160179646A1

公开(公告)日：2016-06-23

申请号：US14580588

申请日：2014-12-23

申请人： Michael Neve De Mevergnies ,  Hermann W. Gartler ,  Michael S. Bair

发明人： Michael Neve De Mevergnies ,  Hermann W. Gartler ,  Michael S. Bair

IPC分类号： G06F11/25 ,  G06F11/27

CPC分类号： G01R31/31719 ,  G01R31/31705 ,  G01R31/3177 ,  G06F11/00 ,  G06F11/25 ,  G06F11/27

摘要： A chassis platform, such as processor or a system-on-chip (SoC), includes logic to implement a debug chassis security system including a policy generator to control access from a test access port. The policy generator may distribute a debug policy to at least one logic block that locally enforces the debug policy. The debug policy may include a delayed authentication policy in which debug assets are distributed and the chassis platform is initially locked to prevent debug access via the test access port. An authenticated debug user may unlock the chassis platform at a later time to enable debugging operations. The debug policy may also include a live execution policy and an immediate debug policy.

摘要翻译： 诸如处理器或片上系统（SoC）的底盘平台包括实现包括策略生成器的调试机箱安全系统的逻辑，以控制来自测试访问端口的访问。 策略生成器可以将调试策略分发到在本地强制调试策略的至少一个逻辑块。 调试策略可以包括延迟的认证策略，其中分发调试资产，并且机箱平台最初被锁定以防止经由测试访问端口的调试访问。 经验证的调试用户可以稍后解锁机箱平台，以启用调试操作。 调试策略还可以包括实时执行策略和即时调试策略。

公开(公告)号：US09524263B2

公开(公告)日：2016-12-20

申请号：US13538463

申请日：2012-06-29

申请人： Robert S. Chappell ,  John W. Faistl ,  Hermann W. Gartler ,  Michael D. Tucknott ,  Rajesh S. Parathasarthy ,  David W. Burns

发明人： Robert S. Chappell ,  John W. Faistl ,  Hermann W. Gartler ,  Michael D. Tucknott ,  Rajesh S. Parathasarthy ,  David W. Burns

IPC分类号： G06F13/42 ,  G06F9/52 ,  G06F12/08 ,  G06F12/12

CPC分类号： G06F12/1491 ,  G06F9/52 ,  G06F9/526 ,  G06F12/0815 ,  G06F12/0842 ,  G06F12/0862 ,  G06F12/126 ,  G06F12/1466 ,  G06F13/42 ,  G06F2212/1052 ,  G06F2212/602

摘要： A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.

摘要翻译： 描述了一种包括检测线程的指令是锁定指令的方法。 该指令还包括确定所述指令的执行包括施加总线锁定。 该指令还包括响应于所述确定执行总线锁定辅助功能，所述总线锁定辅助功能包括除了总线锁定协议的实现之外的与所述总线锁相关联的功能。

公开(公告)号：US20150127983A1

公开(公告)日：2015-05-07

申请号：US13997182

申请日：2010-12-23

申请人： Mark B. Trobough ,  Keshavan K. Tiruvallur ,  Chinna B. Prudvi ,  Christian E. Iovin ,  David W. Grawrock ,  Jay J. Nejedlo ,  Ashok N. Kabadi ,  Travis K. Goff ,  Evan J. Halprin ,  Kapila B. Udawatta ,  Jiun Long Foo ,  Wee Hoo Cheah ,  Vui Yong Liew ,  Selvakumar Raja Gopal ,  Yuen Tat Lee ,  Samie B. Samaan ,  Kip C. Killpack ,  Neil Dobler ,  Nagib Z. Hakim ,  Briar Meyer ,  William H. Penner ,  John L. Baudrexl ,  Russell J. Wunderlich ,  James J. Grealish ,  Kyle Markley ,  Timothy S. Storey ,  Loren J. McConnell ,  Lyle E. Cool ,  Mukesh Kataria ,  Rahima K. Mohammed ,  Tieyu Zheng ,  Yi Amy Xia ,  Ridvan A. Sahan ,  Arun R. Ramadorai ,  Priyadarsan Patra ,  Edwin E. Parks ,  Abhijit Davare ,  Padmakumar Gopal ,  Bruce Querbach ,  Hermann W. Gartler ,  Keith Drescher ,  Sanjay S. Salem ,  David C. Florey

发明人： Mark B. Trobough ,  Keshavan K. Tiruvallur ,  Chinna B. Prudvi ,  Christian E. Iovin ,  David W. Grawrock ,  Jay J. Nejedlo ,  Ashok N. Kabadi ,  Travis K. Goff ,  Evan J. Halprin ,  Kapila B. Udawatta ,  Jiun Long Foo ,  Wee Hoo Cheah ,  Vui Yong Liew ,  Selvakumar Raja Gopal ,  Yuen Tat Lee ,  Samie B. Samaan ,  Kip C. Killpack ,  Neil Dobler ,  Nagib Z. Hakim ,  Briar Meyer ,  William H. Penner ,  John L. Baudrexl ,  Russell J. Wunderlich ,  James J. Grealish ,  Kyle Markley ,  Timothy S. Storey ,  Loren J. McConnell ,  Lyle E. Cool ,  Mukesh Kataria ,  Rahima K. Mohammed ,  Tieyu Zheng ,  Yi Amy Xia ,  Ridvan A. Sahan ,  Arun R. Ramadorai ,  Priyadarsan Patra ,  Edwin E. Parks ,  Abhijit Davare ,  Padmakumar Gopal ,  Bruce Querbach ,  Hermann W. Gartler ,  Keith Drescher ,  Sanjay S. Salem ,  David C. Florey

IPC分类号： G06F11/273

CPC分类号： G06F11/2733 ,  G06F11/267

摘要： An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

摘要翻译： 这里描述了一种用于提供测试，验证和调试架构的装置和方法。 在目标或基础级别，硬件（测试设计或DFx）被设计并集成在硅部件中。 控制器可以提供对这种钩子的抽象访问，例如通过抽象层来抽象硬件DFx的低级细节。 此外，通过接口（如API）的抽象层向更高级的软件/表示层提供服务，例程和数据结构，这些层能够收集测试数据，以便对被测单元/平台进行验证和调试。 此外，该架构可能提供对测试架构的分层（多级）安全访问。 此外，可以通过使用统一的双向测试访问端口来简化对平台的测试架构的物理访问，同时还可能允许远程访问执行被测部件/平台的远程测试和脱离。 本质上描述了一个完整的测试架构栈，用于电子部件，设备和平台的测试，验证和调试。

公开(公告)号：US08683158B2

公开(公告)日：2014-03-25

申请号：US11322756

申请日：2005-12-30

申请人： Martin G. Dixon ,  David A. Koufaty ,  Camron B. Rust ,  Hermann W. Gartler ,  Frank Binns

发明人： Martin G. Dixon ,  David A. Koufaty ,  Camron B. Rust ,  Hermann W. Gartler ,  Frank Binns

IPC分类号： G06F12/14

CPC分类号： G06F12/1425 ,  G06F12/1491

摘要： Apparatuses and methods for steering SMM code region accesses are disclosed. In one embodiment, an apparatus includes a status indicator, a base storage location, and an abort storage location. The status indicator is to indicate whether the apparatus is operating in SMM. The base storage location is to store a base address and the abort storage location is to store an abort address. The base address is to specify a first memory address region at which SMM code is to be accessed. The abort address is to specify a second memory address region to which accesses to the first memory address region are to be steered if the apparatus is not operating in SMM.

摘要翻译： 公开了用于转向SMM码区域访问的装置和方法。 在一个实施例中，装置包括状态指示符，基本存储位置和中止存储位置。 状态指示灯是指示设备是否在SMM中运行。 基本存储位置是存储基地址，并且中止存储位置是存储中止地址。 基地址是指定要访问SMM代码的第一个存储器地址区域。 中止地址是指定第二存储器地址区域，如果设备不在SMM中操作，则对第一存储器地址区域进行访问将被转向。

公开(公告)号：US10198333B2

公开(公告)日：2019-02-05

申请号：US13997182

申请日：2010-12-23

申请人： Mark B. Trobough ,  Keshavan K. Tiruvallur ,  Chinna B. Prudvi ,  Christian E. Iovin ,  David W. Grawrock ,  Jay J. Nejedlo ,  Ashok N. Kabadi ,  Travis K. Goff ,  Evan J. Halprin ,  Kapila B. Udawatta ,  Jiun Long Foo ,  Wee Hoo Cheah ,  Vui Yong Liew ,  Selvakumar Raja Gopal ,  Yuen Tat Lee ,  Samie B. Samaan ,  Kip C. Killpack ,  Neil Dobler ,  Nagib Z. Hakim ,  Brian Meyer ,  William H. Penner ,  John L. Baudrexl ,  Russell J. Wunderlich ,  James J. Grealish ,  Kyle Markley ,  Timothy S. Storey ,  Loren J. McConnell ,  Lyle E. Cool ,  Mukesh Kataria ,  Rahima K. Mohammed ,  Tieyu Zheng ,  Yi Amy Xia ,  Ridvan A. Sahan ,  Arun R. Ramadorai ,  Priyadarsan Patra ,  Edwin E. Parks ,  Abhijit Davare ,  Padmakumar Gopal ,  Bruce Querbach ,  Hermann W. Gartler ,  Keith Drescher ,  Sanjay S. Salem ,  David C. Florey

发明人： Mark B. Trobough ,  Keshavan K. Tiruvallur ,  Chinna B. Prudvi ,  Christian E. Iovin ,  David W. Grawrock ,  Jay J. Nejedlo ,  Ashok N. Kabadi ,  Travis K. Goff ,  Evan J. Halprin ,  Kapila B. Udawatta ,  Jiun Long Foo ,  Wee Hoo Cheah ,  Vui Yong Liew ,  Selvakumar Raja Gopal ,  Yuen Tat Lee ,  Samie B. Samaan ,  Kip C. Killpack ,  Neil Dobler ,  Nagib Z. Hakim ,  Brian Meyer ,  William H. Penner ,  John L. Baudrexl ,  Russell J. Wunderlich ,  James J. Grealish ,  Kyle Markley ,  Timothy S. Storey ,  Loren J. McConnell ,  Lyle E. Cool ,  Mukesh Kataria ,  Rahima K. Mohammed ,  Tieyu Zheng ,  Yi Amy Xia ,  Ridvan A. Sahan ,  Arun R. Ramadorai ,  Priyadarsan Patra ,  Edwin E. Parks ,  Abhijit Davare ,  Padmakumar Gopal ,  Bruce Querbach ,  Hermann W. Gartler ,  Keith Drescher ,  Sanjay S. Salem ,  David C. Florey

IPC分类号： G06F11/273 ,  G06F11/267

摘要： An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

公开(公告)号：US09430347B2

公开(公告)日：2016-08-30

申请号：US14580588

申请日：2014-12-23

申请人： Michael Neve De Mevergnies ,  Hermann W. Gartler ,  Michael S. Bair

发明人： Michael Neve De Mevergnies ,  Hermann W. Gartler ,  Michael S. Bair

IPC分类号： H04L29/06 ,  G06F11/25 ,  G06F11/27

CPC分类号： G01R31/31719 ,  G01R31/31705 ,  G01R31/3177 ,  G06F11/00 ,  G06F11/25 ,  G06F11/27

摘要： A chassis platform, such as processor or a system-on-chip (SoC), includes logic to implement a debug chassis security system including a policy generator to control access from a test access port. The policy generator may distribute a debug policy to at least one logic block that locally enforces the debug policy. The debug policy may include a delayed authentication policy in which debug assets are distributed and the chassis platform is initially locked to prevent debug access via the test access port. An authenticated debug user may unlock the chassis platform at a later time to enable debugging operations. The debug policy may also include a live execution policy and an immediate debug policy.

摘要翻译： 诸如处理器或片上系统（SoC）的底盘平台包括实现包括策略生成器的调试机箱安全系统的逻辑，以控制来自测试访问端口的访问。 策略生成器可以将调试策略分发到在本地强制调试策略的至少一个逻辑块。 调试策略可以包括延迟的认证策略，其中分发调试资产，并且机箱平台最初被锁定以防止经由测试访问端口的调试访问。 经验证的调试用户可以稍后解锁机箱平台，以启用调试操作。 调试策略还可以包括实时执行策略和即时调试策略。

公开(公告)号：US20140006661A1

公开(公告)日：2014-01-02

申请号：US13538463

申请日：2012-06-29

申请人： Robert S. Chappell ,  John W. Faistl ,  Hermann W. Gartler ,  Michael D. Tucknott ,  Rajesh S. Parathasarthy ,  David W. Burns

发明人： Robert S. Chappell ,  John W. Faistl ,  Hermann W. Gartler ,  Michael D. Tucknott ,  Rajesh S. Parathasarthy ,  David W. Burns

IPC分类号： G06F13/42

CPC分类号： G06F12/1491 ,  G06F9/52 ,  G06F9/526 ,  G06F12/0815 ,  G06F12/0842 ,  G06F12/0862 ,  G06F12/126 ,  G06F12/1466 ,  G06F13/42 ,  G06F2212/1052 ,  G06F2212/602

摘要： A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.

摘要翻译： 描述了一种包括检测线程的指令是锁定指令的方法。 该指令还包括确定所述指令的执行包括施加总线锁定。 该指令还包括响应于所述确定执行总线锁定辅助功能，所述总线锁定辅助功能包括除了总线锁定协议的实现之外的与所述总线锁相关联的功能。

公开(公告)号：US07502892B2

公开(公告)日：2009-03-10

申请号：US10747145

申请日：2003-12-30

申请人： Per H. Hammarlund ,  Hermann W. Gartler

发明人： Per H. Hammarlund ,  Hermann W. Gartler

IPC分类号： G06F12/00

CPC分类号： G06F9/383 ,  G06F9/3834 ,  G06F12/0804 ,  G06F12/0831 ,  Y02D10/13

摘要： Embodiments of the present invention relate to cache coherency. In an embodiment of the invention, a cache includes one or more cache lines. A store pipeline may retrieve a tag associated with one of the cache lines. The data associated with the cache line may not retrieved and the cache line may be updated if, based on the tag, the cache line is determined to be in a modified or exclusive state.

摘要翻译： 本发明的实施例涉及高速缓存一致性。 在本发明的实施例中，高速缓存包括一个或多个高速缓存行。 存储流水线可以检索与一个缓存行相关联的标签。 如果基于标签将高速缓存行确定为处于修改或排除状态，则可能无法检索与高速缓存行相关联的数据，并且可以更新高速缓存行。