公开(公告)号：US20150127983A1

公开(公告)日：2015-05-07

申请号：US13997182

申请日：2010-12-23

申请人： Mark B. Trobough ,  Keshavan K. Tiruvallur ,  Chinna B. Prudvi ,  Christian E. Iovin ,  David W. Grawrock ,  Jay J. Nejedlo ,  Ashok N. Kabadi ,  Travis K. Goff ,  Evan J. Halprin ,  Kapila B. Udawatta ,  Jiun Long Foo ,  Wee Hoo Cheah ,  Vui Yong Liew ,  Selvakumar Raja Gopal ,  Yuen Tat Lee ,  Samie B. Samaan ,  Kip C. Killpack ,  Neil Dobler ,  Nagib Z. Hakim ,  Briar Meyer ,  William H. Penner ,  John L. Baudrexl ,  Russell J. Wunderlich ,  James J. Grealish ,  Kyle Markley ,  Timothy S. Storey ,  Loren J. McConnell ,  Lyle E. Cool ,  Mukesh Kataria ,  Rahima K. Mohammed ,  Tieyu Zheng ,  Yi Amy Xia ,  Ridvan A. Sahan ,  Arun R. Ramadorai ,  Priyadarsan Patra ,  Edwin E. Parks ,  Abhijit Davare ,  Padmakumar Gopal ,  Bruce Querbach ,  Hermann W. Gartler ,  Keith Drescher ,  Sanjay S. Salem ,  David C. Florey

发明人： Mark B. Trobough ,  Keshavan K. Tiruvallur ,  Chinna B. Prudvi ,  Christian E. Iovin ,  David W. Grawrock ,  Jay J. Nejedlo ,  Ashok N. Kabadi ,  Travis K. Goff ,  Evan J. Halprin ,  Kapila B. Udawatta ,  Jiun Long Foo ,  Wee Hoo Cheah ,  Vui Yong Liew ,  Selvakumar Raja Gopal ,  Yuen Tat Lee ,  Samie B. Samaan ,  Kip C. Killpack ,  Neil Dobler ,  Nagib Z. Hakim ,  Briar Meyer ,  William H. Penner ,  John L. Baudrexl ,  Russell J. Wunderlich ,  James J. Grealish ,  Kyle Markley ,  Timothy S. Storey ,  Loren J. McConnell ,  Lyle E. Cool ,  Mukesh Kataria ,  Rahima K. Mohammed ,  Tieyu Zheng ,  Yi Amy Xia ,  Ridvan A. Sahan ,  Arun R. Ramadorai ,  Priyadarsan Patra ,  Edwin E. Parks ,  Abhijit Davare ,  Padmakumar Gopal ,  Bruce Querbach ,  Hermann W. Gartler ,  Keith Drescher ,  Sanjay S. Salem ,  David C. Florey

IPC分类号： G06F11/273

CPC分类号： G06F11/2733 ,  G06F11/267

摘要： An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

摘要翻译： 这里描述了一种用于提供测试，验证和调试架构的装置和方法。 在目标或基础级别，硬件（测试设计或DFx）被设计并集成在硅部件中。 控制器可以提供对这种钩子的抽象访问，例如通过抽象层来抽象硬件DFx的低级细节。 此外，通过接口（如API）的抽象层向更高级的软件/表示层提供服务，例程和数据结构，这些层能够收集测试数据，以便对被测单元/平台进行验证和调试。 此外，该架构可能提供对测试架构的分层（多级）安全访问。 此外，可以通过使用统一的双向测试访问端口来简化对平台的测试架构的物理访问，同时还可能允许远程访问执行被测部件/平台的远程测试和脱离。 本质上描述了一个完整的测试架构栈，用于电子部件，设备和平台的测试，验证和调试。

公开(公告)号：US10198333B2

公开(公告)日：2019-02-05

申请号：US13997182

申请日：2010-12-23

申请人： Mark B. Trobough ,  Keshavan K. Tiruvallur ,  Chinna B. Prudvi ,  Christian E. Iovin ,  David W. Grawrock ,  Jay J. Nejedlo ,  Ashok N. Kabadi ,  Travis K. Goff ,  Evan J. Halprin ,  Kapila B. Udawatta ,  Jiun Long Foo ,  Wee Hoo Cheah ,  Vui Yong Liew ,  Selvakumar Raja Gopal ,  Yuen Tat Lee ,  Samie B. Samaan ,  Kip C. Killpack ,  Neil Dobler ,  Nagib Z. Hakim ,  Brian Meyer ,  William H. Penner ,  John L. Baudrexl ,  Russell J. Wunderlich ,  James J. Grealish ,  Kyle Markley ,  Timothy S. Storey ,  Loren J. McConnell ,  Lyle E. Cool ,  Mukesh Kataria ,  Rahima K. Mohammed ,  Tieyu Zheng ,  Yi Amy Xia ,  Ridvan A. Sahan ,  Arun R. Ramadorai ,  Priyadarsan Patra ,  Edwin E. Parks ,  Abhijit Davare ,  Padmakumar Gopal ,  Bruce Querbach ,  Hermann W. Gartler ,  Keith Drescher ,  Sanjay S. Salem ,  David C. Florey

发明人： Mark B. Trobough ,  Keshavan K. Tiruvallur ,  Chinna B. Prudvi ,  Christian E. Iovin ,  David W. Grawrock ,  Jay J. Nejedlo ,  Ashok N. Kabadi ,  Travis K. Goff ,  Evan J. Halprin ,  Kapila B. Udawatta ,  Jiun Long Foo ,  Wee Hoo Cheah ,  Vui Yong Liew ,  Selvakumar Raja Gopal ,  Yuen Tat Lee ,  Samie B. Samaan ,  Kip C. Killpack ,  Neil Dobler ,  Nagib Z. Hakim ,  Brian Meyer ,  William H. Penner ,  John L. Baudrexl ,  Russell J. Wunderlich ,  James J. Grealish ,  Kyle Markley ,  Timothy S. Storey ,  Loren J. McConnell ,  Lyle E. Cool ,  Mukesh Kataria ,  Rahima K. Mohammed ,  Tieyu Zheng ,  Yi Amy Xia ,  Ridvan A. Sahan ,  Arun R. Ramadorai ,  Priyadarsan Patra ,  Edwin E. Parks ,  Abhijit Davare ,  Padmakumar Gopal ,  Bruce Querbach ,  Hermann W. Gartler ,  Keith Drescher ,  Sanjay S. Salem ,  David C. Florey

IPC分类号： G06F11/273 ,  G06F11/267

摘要： An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

公开(公告)号：US4850883A

公开(公告)日：1989-07-25

申请号：US53270

申请日：1987-05-21

申请人： Ashok N. Kabadi

发明人： Ashok N. Kabadi

IPC分类号： H01R12/62 ,  H05K3/36

CPC分类号： H01R12/62 ,  H01R12/772 ,  H05K3/365

摘要： A clamping system for use in connecting high density flexible circuit to a rigid printed circuit board. The clamping system utilizes metal-on-elastomer (MOE) strips contained in a MOE holder and held in place by clamping components to provide electrical connections between the high density flexible circuit and the rigid printed circuit board. The clamping system utilizes a flexible mouth surrounding the high density flexible circuit to alleviate stress on the high density flexible circuit, a special plating on the conductors of the high density flexible circuit to prevent oxidation, and a stiffener clamp to provide stability for the MOE strips.

摘要翻译： 一种用于将高密度柔性电路连接到刚性印刷电路板的夹紧系统。 夹紧系统使用包含在MOE夹持器中的金属弹性体（MOE）条，并通过夹紧部件保持在适当位置，以提供高密度柔性电路和刚性印刷电路板之间的电连接。 夹紧系统使用围绕高密度柔性电路的柔性口，以缓解高密度柔性电路上的应力，在高密度柔性电路的导体上进行特殊电镀以防止氧化，以及加强夹具为MOE带提供稳定性 。

公开(公告)号：US06529385B1

公开(公告)日：2003-03-04

申请号：US09382348

申请日：1999-08-25

申请人： Gary W. Brady ,  Harry L. Hampton, III ,  Michael T. White ,  Ashok N. Kabadi

发明人： Gary W. Brady ,  Harry L. Hampton, III ,  Michael T. White ,  Ashok N. Kabadi

IPC分类号： H05K116

CPC分类号： H05K1/023 ,  H05K3/301 ,  H05K2201/10325 ,  H05K2201/10424 ,  H05K2201/10636 ,  H05K2201/10734 ,  Y02P70/611

摘要： Apparatus and methods for connecting a device to an integrated circuit. The apparatus includes an insulating substrate that has two major sides and a number of sites for housing components. Each site has a first node on one of the two sides of the insulating substrate and a second node on the other of the two sides of the insulating substrate. Each site also has components that are aligned normal to the sides of the insulating substrate and are connected to the nodes at the site. Such apparatus are useful as adapters for testing an integrated circuit, such as connecting a test device to the integrated circuit with the adapter and observing and/or driving signals through the adapter.

摘要翻译： 用于将装置连接到集成电路的装置和方法。 该装置包括具有两个主要侧面和多个用于容纳部件的部位的绝缘基板。 每个位置在绝缘基板的两侧中的一侧上具有第一节点，在绝缘基板的两侧的另一侧上具有第二节点。 每个站点还具有与绝缘基板的侧面垂直对准并且连接到现场的节点的部件。 这种装置可用作用于测试集成电路的适配器，例如将测试装置与适配器连接到集成电路，并通过适配器观察和/或驱动信号。

公开(公告)号：US06269864B1

公开(公告)日：2001-08-07

申请号：US09504019

申请日：2000-02-18

申请人： Ashok N. Kabadi

发明人： Ashok N. Kabadi

IPC分类号： F28F700

CPC分类号： H01L23/3672 ,  F28F3/022 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A heat sink for a microprocessor includes a thermally conductive base having a plurality of fin structures upwardly extending from the thermally conductive base. The plurality of fin structures having a first surface comprising a plurality of surface area enhancer structures to increase a convection surface area of the heat sink for a given volume of a heat sink to enhance heat dissipation from the heat sink.

摘要翻译： 用于微处理器的散热器包括具有从导热基部向上延伸的多个翅片结构的导热基座。 多个翅片结构具有包括多个表面积增强器结构的第一表面，以增加用于给定体积的散热器的散热器的对流表面积，以增强散热器的散热。

公开(公告)号：US4917613A

公开(公告)日：1990-04-17

申请号：US267028

申请日：1988-11-04

申请人： Ashok N. Kabadi

发明人： Ashok N. Kabadi

IPC分类号： H01R12/62 ,  H01R12/77 ,  H05K1/11 ,  H05K1/14 ,  H05K3/00 ,  H05K3/28

CPC分类号： H01R12/62 ,  H05K1/0281 ,  H05K1/118 ,  H01R12/772 ,  H05K1/14 ,  H05K2201/053 ,  H05K2201/056 ,  H05K2201/10325 ,  H05K2201/2009 ,  H05K3/0058 ,  H05K3/281

摘要： A connector system for coupling electrical cables with electrical apparatus such as integrated circuits and printed circuit boards. The present invention discloses a connector system for coupling electrical cables, preferably high density flexible circuits, with electrical apparatus. The connection system discloses a stiffener plate having a slot therein cut at a 45 degree angle from one corner of the stiffener plate to a second distal point of the stiffener plate. A pair of flexible circuits may be disposed in the stiffener plate and bent at 90 degree angles to the plate for coupling to a surface of the stiffener plate. The flexible circuits are of a design allowing for placement of electrical conductive pads along four edges of the stiffener plate, thus maximizing the density of electrical connections in the connection system.

摘要翻译： 用于将电缆与诸如集成电路和印刷电路板的电气设备耦合的连接器系统。 本发明公开了一种用于将电缆（优选高密度柔性电路）与电气设备耦合的连接器系统。 连接系统公开了一种加强板，其具有从加强板的一个角部到加强板的第二远点45度角切割的槽。 一对柔性电路可以设置在加强板中并与板成90度角弯曲，以耦合到加强板的表面。 柔性电路具有允许沿着加强板​​的四个边缘布置导电焊盘的设计，从而使连接系统中的电连接的密度最大化。

公开(公告)号：US5057023A

公开(公告)日：1991-10-15

申请号：US532015

申请日：1990-06-01

申请人： Ashok N. Kabadi ,  Leonard O. Turner ,  Ronald C. Flamm

发明人： Ashok N. Kabadi ,  Leonard O. Turner ,  Ronald C. Flamm

IPC分类号： H05K1/14 ,  H05K1/18 ,  H05K3/32

CPC分类号： H01R12/62 ,  H05K3/326 ,  H05K1/141 ,  H05K1/189 ,  H05K2201/10393 ,  H05K2201/10689 ,  Y10S439/912

摘要： A connection system for use in connecting a high density flexible circuit directly to a surface mounted integrated circuit component mounted on a printed circuit board. The connection system utilizes an upper and lower stiffener plate to route the contacts of the high density flexible circuit to the pins of the integrated circuit component. The connection system utilizes silicone rubber pressure rods to create a force on the contacts of the higher density flexible circuit to ensure reliable connection to the leads of the surface mounted components. The connection system utilizes comb spacers which define slots to align the contacts of the high density circuit to the pins of the integrated circuit component and a top clamp to retain the assembly onto the integrated circuit component.

摘要翻译： 一种用于将高密度柔性电路直接连接到安装在印刷电路板上的表面安装集成电路部件的连接系统。 连接系统利用上下加强板将高密度柔性电路的触头引导到集成电路部件的引脚。 连接系统利用硅橡胶压力杆在较高密度柔性电路的触点上产生力，以确保与表面安装部件的引线的可靠连接。 连接系统使用梳形间隔件，其限定狭槽以将高密度电路的触点与集成电路部件的引脚对准，以及顶部钳位件，以将组件保持在集成电路部件上。

公开(公告)号：US07177142B2

公开(公告)日：2007-02-13

申请号：US10955676

申请日：2004-09-29

申请人： Ashok N. Kabadi ,  Frank R. DeWeese

发明人： Ashok N. Kabadi ,  Frank R. DeWeese

IPC分类号： H05K7/20 ,  G01R1/073

CPC分类号： H05K7/1007 ,  H01R12/585 ,  H01R12/7052 ,  H01R12/7064 ,  H01R12/7076 ,  H05K3/301 ,  H05K3/308 ,  H05K3/325 ,  H05K2201/10325 ,  H05K2201/10704 ,  H05K2201/10719

摘要： The apparatus and method described herein are for coupling an integrated circuit to a circuit board, while eliminating the need for a backing plate, when a compression socket is utilized. A plurality of tension pins are coupled to an integrated circuit for engaging a plurality of corresponding barrels in a circuit board to compress a compression socket to make an electrical connection between the integrated circuit and the circuit board.

摘要翻译： 当使用压缩插座时，本文描述的装置和方法用于将集成电路耦合到电路板，同时消除对背板的需要。 多个张紧销耦合到集成电路，用于接合电路板中的多个对应的筒以压缩压缩插座以在集成电路和电路板之间形成电连接。

公开(公告)号：US6097609A

公开(公告)日：2000-08-01

申请号：US223647

申请日：1998-12-30

申请人： Ashok N. Kabadi

发明人： Ashok N. Kabadi

IPC分类号： H05K7/10 ,  H05K7/02

CPC分类号： H05K7/1061

摘要： An electronic packaging assembly is disclosed. An electronic component is disposed on a socketing substrate utilizing a ball grid array or land grid array. The socketing substrate contains a series of pins that are embedded within the thickness of the socketing substrate. The pins correspond with the ball grid array or land grid array contacts of the electronic component. The socketing substrate is mounted onto a motherboard using an array of solder balls that correspond to and are disposed on, the end of the pins facing the motherboard. If desired, the electronic component may be protected by a metal lid. If desired, socketing substrates can be disposed on both sides of a motherboard.

摘要翻译： 公开了一种电子包装组件。 使用球栅阵列或平台栅格阵列将电子部件设置在袜子基底上。 浸渍基材包含一系列嵌入在浸渍基材的厚度内的销。 引脚对应于电子部件的球栅阵列或焊盘网格阵列触点。 使用与面向母板的销的端部对应并且布置在其上的焊球阵列将堆积的基板安装到母板上。 如果需要，电子部件可以被金属盖保护。 如果需要，可以在母板的两侧设置插入基板。

公开(公告)号：US4798918A

公开(公告)日：1989-01-17

申请号：US99259

申请日：1987-09-21

申请人： Ashok N. Kabadi ,  Leonard O. Turner ,  Michael T. White

发明人： Ashok N. Kabadi ,  Leonard O. Turner ,  Michael T. White

IPC分类号： H01B7/08 ,  H05K1/00 ,  H05K1/02 ,  H05K3/28

CPC分类号： H01B7/0838 ,  H05K1/0219 ,  H05K1/0393 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09672 ,  H05K3/281

摘要： A high density flexible circuit for coupling electrical devices. The flexible circuit has signal and ground traces on both sides of the flexible circuit. Each signal trace is surrounded by ground traces. There is a ground trace on either side of each signal trace and two ground traces located below each signal trace. This system of placing ground traces surrounding each signal trace reduces electrical noise between the signal traces and reduces the electrical capacitance of the circuit.

摘要翻译： 用于耦合电气设备的高密度柔性电路。 柔性电路在柔性电路的两侧都有信号和接地迹线。 每个信号迹线都被接地迹线包围。 在每个信号迹线的两侧都有一个接地迹线，位于每个信号迹线下方的两个接地迹线。 围绕每个信号迹线放置接地迹线的系统降低了信号迹线之间的电噪声并降低了电路的电容。