公开(公告)号：US20060001045A1

公开(公告)日：2006-01-05

申请号：US10883091

申请日：2004-07-01

申请人： Lakhbeer Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John Turner

发明人： Lakhbeer Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John Turner

IPC分类号： H01L29/739 ,  H01L27/10 ,  G11C16/04 ,  G11C11/34

CPC分类号： G11C11/412 ,  H01L27/0207 ,  H01L27/11807

摘要： A configuration memory cell (“CRAM”) for a field programmable gate array (“FPGA”) integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.

摘要翻译： 用于现场可编程门阵列（“FPGA”）集成电路（“IC”）器件的配置存储单元（“CRAM”）被赋予增加的对单一事件不正常（“SEU”）的阻力。 CRAM的输入节点的栅极结构的一部分相对于栅极结构的其余部分的标称尺寸增大。 放大栅极结构的一部分位于与IC的N阱区电容性相邻的位置，另一部分位于与IC的P阱区电容相邻的位置。 这种布置使得输入节点增加了抵抗SEU的电容，而与输入节点的逻辑电平无关。 本发明也可应用于任何类型的存储器单元的任何节点，其对期望增加的对SEU的抗性。

公开(公告)号：US20080074145A1

公开(公告)日：2008-03-27

申请号：US11951122

申请日：2007-12-05

申请人： Lakhbeer Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John Turner

发明人： Lakhbeer Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John Turner

IPC分类号： H03K19/173

CPC分类号： G11C11/412 ,  H01L27/0207 ,  H01L27/11807

摘要： A configuration memory cell (“CRAM”) for a field programmable gate array (“FPGA”) integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.

摘要翻译： 用于现场可编程门阵列（“FPGA”）集成电路（“IC”）器件的配置存储单元（“CRAM”）被赋予增加的对单一事件不正常（“SEU”）的阻力。 CRAM的输入节点的栅极结构的一部分相对于栅极结构的其余部分的标称尺寸增大。 放大栅极结构的一部分位于与IC的N阱区电容性相邻的位置，另一部分位于与IC的P阱区电容相邻的位置。 这种布置使得输入节点增加了抵抗SEU的电容，而与输入节点的逻辑电平无关。 本发明也可应用于任何类型的存储器单元的任何节点，其对期望增加的对SEU的抗性。

公开(公告)号：US07200824B1

公开(公告)日：2007-04-03

申请号：US10990663

申请日：2004-11-16

申请人： Lakhbeer Sidhu ,  Irfan Rahim

发明人： Lakhbeer Sidhu ,  Irfan Rahim

IPC分类号： G06F17/50 ,  G06F19/00 ,  H03K19/003 ,  H01L25/00

CPC分类号： G06F17/5068 ,  G06F17/504 ,  G06F2217/78 ,  G06F2217/84

摘要： Methods and apparatus are provided for harnessing the effects of process variations in a semiconductor device. In one example, implementing an electronic design based on collected performance parameters is provided. In general, a core is segmented into multiple core regions. A performance parameter can be collected from each of the core regions. The performance parameter can be collected with a performance measuring mechanism associated with the core region. The performance parameter can be correlated to the performance requirements of an electronic device portion, and the electronic design portion can be implemented in a core region that has a performance parameter matched to the needs of the electronic design portion. In this way, process variation effects are harnessed by optimizing the implementation of the electronic design in regions of the semiconductor device best suited the needs of each electronic design portion. Therefore, performance/power optimization of the semiconductor device can be realized.

摘要翻译： 提供了用于利用半导体器件中工艺变化的影响的方法和装置。 在一个示例中，提供了基于收集的性能参数实现电子设计。 通常，核心被分割成多个核心区域。 可以从每个核心区域收集性能参数。 可以使用与核心区域相关联的性能测量机制来收集性能参数。 性能参数可以与电子设备部分的性能要求相关联，并且电子设计部分可以在具有与电子设计部分的需要匹配的性能参数的核心区域中实现。 以这种方式，通过优化在最适合每个电子设计部分的需要的半导体器件的区域中电子设计的实现来利用工艺变化效应。 因此，可以实现半导体器件的性能/功率优化。